30 research outputs found

    Locality and Singularity for Store-Atomic Memory Models

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    Robustness is a correctness notion for concurrent programs running under relaxed consistency models. The task is to check that the relaxed behavior coincides (up to traces) with sequential consistency (SC). Although computationally simple on paper (robustness has been shown to be PSPACE-complete for TSO, PGAS, and Power), building a practical robustness checker remains a challenge. The problem is that the various relaxations lead to a dramatic number of computations, only few of which violate robustness. In the present paper, we set out to reduce the search space for robustness checkers. We focus on store-atomic consistency models and establish two completeness results. The first result, called locality, states that a non-robust program always contains a violating computation where only one thread delays commands. The second result, called singularity, is even stronger but restricted to programs without lightweight fences. It states that there is a violating computation where a single store is delayed. As an application of the results, we derive a linear-size source-to-source translation of robustness to SC-reachability. It applies to general programs, regardless of the data domain and potentially with an unbounded number of threads and with unbounded buffers. We have implemented the translation and verified, for the first time, PGAS algorithms in a fully automated fashion. For TSO, our analysis outperforms existing tools

    Photoreceptor glucose metabolism determines normal retinal vascular growth

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    Abstract The neural cells and factors determining normal vascular growth are not well defined even though vision‐threatening neovessel growth, a major cause of blindness in retinopathy of prematurity (ROP) (and diabetic retinopathy), is driven by delayed normal vascular growth. We here examined whether hyperglycemia and low adiponectin (APN) levels delayed normal retinal vascularization, driven primarily by dysregulated photoreceptor metabolism. In premature infants, low APN levels correlated with hyperglycemia and delayed retinal vascular formation. Experimentally in a neonatal mouse model of postnatal hyperglycemia modeling early ROP, hyperglycemia caused photoreceptor dysfunction and delayed neurovascular maturation associated with changes in the APN pathway; recombinant mouse APN or APN receptor agonist AdipoRon treatment normalized vascular growth. APN deficiency decreased retinal mitochondrial metabolic enzyme levels particularly in photoreceptors, suppressed retinal vascular development, and decreased photoreceptor platelet‐derived growth factor (Pdgfb). APN pathway activation reversed these effects. Blockade of mitochondrial respiration abolished AdipoRon‐induced Pdgfb increase in photoreceptors. Photoreceptor knockdown of Pdgfb delayed retinal vascular formation. Stimulation of the APN pathway might prevent hyperglycemia‐associated retinal abnormalities and suppress phase I ROP in premature infants

    Take My Hand: Teaching the Gospel Singer in the Applied Voice Studio

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    KBSE and ada: Object and enabling technology

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    "Layering" is a visualisation technique that enables basic relationships between software system components to be overlaid with the results of more sophisticated design recovery analyses. Layering can be implemented via a simple presentation tool, to which the results of different analysers can be coupled. Knowledge-based analysis technology can be extended to support Ada83-Ada95 conversion. Taking advantage of the self-implementation of the enabling technology, the conversion tool can be involuted so that the enabling technology itself is able to be represented in Ada95

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    A Verification-Based Approach to Memory Fence Insertion in PSO Memory Systems

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    peer reviewedThis paper addresses the problem of verifying and correcting programs when they are moved from a sequential consistency execution environment to a relaxed memory context. Specifically, it considers the PSO (Partial Store Order) memory model, which corresponds to the use of a store buffer for each shared variable and each process. We also will consider, as an intermediate step, the TSO (Total Store Order) memory model, which corresponds to the use of one store buffer per process. The proposed approach extends a previously developed verification tool that uses finite automata to symbolically represent the possible contents of the store buffers. Its starting point is a program that is correct for the usual Sequential Consistency (SC) memory model, but that might be incorrect under PSO with respect to safety properties. This program is then first analyzed and corrected for the TSO memory model, and then this TSO-safe program is analyzed and corrected under PSO, producing a PSO-safe program. To obtain a TSO-safe program, only store-load fences (TSO only allows store-load relaxations) are introduced into the program. Finaly, to produce a PSO-safe program, only store-store fences (PSO additionally allows store-store relaxations) are introduced. An advantage of our technique is that the underlying symbolic verification tool makes a full exploration of program behaviors possible even for cyclic programs, which makes our approach broadly applicable. The method has been tested with an experimental implementation and can effectively handle a series of classical examples
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