A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization

A method for SoC global interconnect characterization is presented. Buses are partitioned in blocks whose electrical characterization is done using reduced size primitives and extending the results to the original structure. The accuracy is measured on typical metrics like delays, crosstalk peaks and reabsorbing time. This work is the basis for an automatic evaluator of interconnect metrics to be used in SoC design space explorations and verification

A Block-Based Approach for SoC global Interconnect Electrical ParamenterCharacterization

The resistance of on-chip interconnects and the current drive of transistors is strongly temperature dependent. As a result, the interconnect performance is affected by the temperature in a sizeable proportion. In this paper we evaluate thermal effects in global RLC interconnects and quantify their impact in a standard optimization procedure in which repeaters are used. By evaluating the difference between a simple RC and an accurate RLC model, we show how the temperature induced increase of resistance may reduce the impact of inductance. We also project the evolution of such effects in future technology nodes, according to the semiconductor roadmap