Comprehensive physical modeling of NMOSFET hot-carrier-induced degradation

The role of hot-carrier-induced interface states in NMOSFETs is discussed. A new model is proposed based on measurements in several 0.7¿m CMOS technologies of different suppliers. Our model for the first time enables accurate interface state prediction over many orders of magnitude in time for all stress conditions under pinch-off and incorporates saturation. It can easily be implemented in a reliability circuit simulator, enabling more accurate NMOSFET parameter degradation calculations(e.g. ¿ID ¿gm etc.)

Component lifetime modelling

There are two approaches to component lifetime modelling. The first one uses a reliability prediction method as described in the (military) handbooks with the appropriate models and parameters. The advantages are: (a) It takes into account all possible failure mechanisms. (b) It is easy to use. The disadvantages are: (a) It assumes a constant failure rate which is often not the case (infant mortality). (b) It contains no designable parameters and therefore it cannot be used for built-in reliability. The second approach is to model the different degradation mechanisms and to incorporate this into an (existing) circuit simulator. Here we have also advantages and disadvantages which are mostly complementary to those of the first method

On the design of a reliability circuit simulator

This paper describes the outcome of a study into the feasibility of a reliability circuit simulator for ICs in general and the critical parameters involved in particular. The necessary conditions are formulated that have to be fulfilled before any construction of the reliability simulator is meaningful or can be done at all. It has been found that failure mechanisms in the wear-out regime meet these conditions. Next, a general approach is given to make a simulator. This approach is actually derived from circuit simulator activities on hot carrier degradation and electromigration, respectively. Finally, the different groups of parameters are defined

Comprehensive physical modeling of NMOSFET hot-carrier-induced degradation

The role of hot-carrier-induced interface states in NMOSFETs is discussed. A new model is proposed based on measurements in several 0.7¿m CMOS technologies of different suppliers. Our model for the first time enables accurate interface state prediction over many orders of magnitude in time for all stress conditions under pinch-off and incorporates saturation. It can easily be implemented in a reliability circuit simulator, enabling more accurate NMOSFET parameter degradation calculations(e.g. ¿ID ¿gm etc.)

Dealing with hot-carrier aging in nMOS and DMOS, models, simulations and characterizations

Circuit aging simulation is seen as a true enhancement to device and circuit simulation. To predict aging of circuit performance, tested models for device parameters are needed in which the change in device behavior as function of time, given the biasing and temperature condition of the device in the circuit, is correctly modeled. The time scale here is the lifetime of the product. A circuit simulator in the transient mode can predict circuit aging using a transformation of the dc/ac biasing situation with an appropriate scaling mechanism. Device aging models that can be implemented in such a circuit simulator are presented here for nMOS and DMOS (double diffused MOS) based on measurements and empirical modeling