3 research outputs found
A broadband multilayer antireflection coating for thin film CdSeTe/CdTe solar cells
Thin film cadmium telluride (CdTe) photovoltaics (PV) is the most successful second-generation PV technology, with a current installed capacity of over 30 GWp, predominantly at utility scale. Recent improvements in the buffer layer of the device, switching from cadmium sulphide (CdS) to transparent magnesium-doped zinc oxide (MZO), tin oxide (SnO2), or zinc oxide (ZnO), and the addition of selenium to the absorber layer, have expanded the wavelength range over which CdTe devices operate, from 400–850 nm to 350–900 nm. These changes have resulted in higher efficiency devices. As a result, an optimized antireflection (AR) coating design is required to improve the efficiency further. A six-layer AR coating of SiO2 and ZrO2, building on a previous four-layer design for CdTe devices, has been designed, modeled, and fabricated on 3.8-mm thick fluorine-doped tin oxide coated TEC™15 substrates, reducing reflection by 3.38% absolute. Electrical measurements of a CdSeTe/CdTe device before and after addition of the AR coating show an increase in short-circuit current density (Jsc) of almost 1 mAcm−2, a relative increase of 3.45%, and a 0.6% increase in the conversion efficiency of the device, from 16.93% to 17.53%, which is a relative increase of 3.54%. Unlike conventional single layer AR coatings this multilayer coating is stable even under the high processing temperatures required in module manufacturing, so could be supplied by glass manufacturers. This newly optimized broadband AR coating on will enable significantly higher conversion efficiencies and help push CdSeTe/CdTe module efficiencies higher.</p
Measurement of band alignment between ZnO based front emitters and CdCl<sub>2</sub> treated CdSeTe/CdTe absorbers
Thin film CdSeTe/CdTe solar cells have achieved > 22% record efficiency and generated solar electricity at a cost as low as 3 US cents per kW.hr in large scale utilities. In this work, the use of ZnO based n-type emitters is considered with the aim of improving the thin film CdSeTe/CdTe photovoltaic device efficiency still further. The measured conduction band offsets (CBOs) between ZnO and CdSeTe are determined to be in the “cliff” conformation. These CBOs will be optimized to achieve a “spike” conformation by incorporating suitable dopants to achieve high device efficiency. This work identifies new pathways to highly efficient ZnO based n-type emitters for arsenic doped CdTe solar cells. In particular, we have identified Sn, Ce and Cs as suitable dopants to generate the preferred ‘spike’ in the band alignment between the emitter layer and the CdSeTe absorber. Suitably doped emitter layers will be used in device research to reduce the deficit in open circuit voltage.</p
Achieving 21.4% efficient CdSeTe/CdTe solar cells using highly resistive intrinsic ZnO buffer layers
In this study, the use of intrinsic and highly insulating ZnO buffer layers to achieve high conversion efficiencies in CdSeTe/CdTe solar cells is reported. The buffer layers are deposited on commercial SnO2:F coated soda‐lime glass substrates and then fabricated into arsenic‐doped CdSeTe/CdTe devices using an absorber and back contact deposited by First Solar. The ZnO thickness is varied from 30 to 200 nm. The devices incorporating a 50 nm ZnO buffer layer achieved an efficiency of 21.23% without an anti‐reflection coating. An improved efficiency of 21.44% is obtained on a substrate with a multilayer anti‐reflection coating deposited prior to device fabrication. The highly efficient ZnO based devices are stable and do not develop anomalous J‐V behavior following environmental tests. High resolution microstructural analysis reveals the formation of a high‐quality ZnO/CdSeTe interface. Unusually, chlorine is not detected as a discrete layer at the interface, these observations point to a high‐quality interface. The extrapolation of Voc to 0 K indicates that interface recombination dominates, suggesting that further improvement is possible. Using device modeling, an attempt is made to understand how this type of device performs so well.</p