SymBIST: Symmetry-based Analog/Mixed-Signal BIST

International audienc

Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP

International audienceIn this paper, we propose a defect-oriented Built-In Self-Test (BIST) paradigm for analog and mixed-signal (A/M-S) Integrated Circuits (ICs), called symmetry-based BIST (Sym-BIST). SymBIST exploits inherent symmetries into the design to generate invariances that should hold true only in defect-free operation. Violation of any of these invariances points to defect detection. We demonstrate SymBIST on a 65nm 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) IP by ST Microelectronics

CAIRO+ : Composants Analogiques Réutilisables

National audienc

Forum on specification and Design Languages

This book brings together a selection of the best papers from the sixteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2013 in Paris, France. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems. • Covers applications of formal methods for specification, verification and debug; • Includes embedded analog and mixed-signal system design; • Enables model-driven engineering for embedded systems design and development

Hierarchical Sizing and Biasing of Analog Firm Intellectual Properties

International audienc

Loop Delay Compensation in Bandpass Continuous-Time Modulators without Additional Feedback Coefficients

International audienceLoop-delay is one of the major sources of instability and signal-to-noise ratio degradation in continuous-time band-pass /spl Sigma//spl Delta/ modulators. In this paper, we use the modified-z-transform technique to calculate the value of the additional feedback coefficient required to compensate for the loop-delay. It is shown that, in certain conditions, this additional feedback coefficient can be removed and the loop-delay is compensated only by modifying the modulator coefficients. This is illustrated by several examples of loop-delay compensation in 2nd, 4th and 6th order bandpass modulators

From filters to transistors A library of analog schematic with automated sizing Team: FOSS EDA for analog and mixed circuit design

International audienceUnlike the digital domain where the use of standard cell libraries considerably reduces the design time, in the analog domain, it is practically impossible to store in the same library all the functions that can cover the entire possible range of data, with all application associated electrical specifications. On the other hand, given the fact that such a library would be very quickly obsolete due to the fast evolution of technologies, it is obvious that without the help of appropriate CAD tools to design parameterized modules, the analog may become a serious bottleneck in terms of design time and cost of a System on Chip

Influence et prise en compte des capacités de diaphonies dans la conception d'outils d'analyse temporelle pour les technologies profondément submicroniques.

National audienceAvec la diminution de la finesse de gravure dans les circuits intégrés, les capacités de couplage entre signaux deviennent nettement supérieures aux capacités par rapport au substrat. Jusqu'à présent dans l'analyse temporelle on pouvait déterminer de façon précise le temps de propagation d'une porte en fonction de trois paramètres: la charge de la porte, l'entrée qui commute et le front d'entrée. Pour des technologies inférieures à 0,35u, la charge apparente de la porte n'est plus connue car elle dépend du comportement des signaux voisins du signal contrôlé par cette porte. De cette constatation découlent deux problèmes : l'extraction des blocs hiérarchiques du circuit lorsqu'on utilise un routage overcell et les implications sur l'analyse temporelle hiérarchique, et le calcul des temps de propagation élémentaires de chaque porte