A Case Study of Self-Checking Circuits Reliability

In this paper, we analyze the reliability of self-checking circuits. A case study is presented in which a fault-tolerant system with duplicated self-checking modules is compared to the TMR version. It is shown that a duplicated self-checking system has a much higher reliability than that of the TMR counterpart. More importantly, the reliability of the selfchecking system does not drop as sharply as that of the TMR version. We also demonstrate the trade-offs between hardware complexity and error handling capability of self-checking circuits. Alternative self-checking designs where some hardware redundancies are removed with the lost of fault-secure and/or self-testing properties are also studied

Single fault masking logic designs with error correcting codes

Triple modular redundancy (TMR) has been the most popular method in reliable logic designs due to its single fault masking capability. However, the reliability of a TMR design can be improved only by enhancing the reliabilities of the components. This paper examines the use of error correcting codes in reliable logic design. The goal is to provide an equivalent single fault masking capability as that of TMR scheme. Further, by reducing the level of hardware redundancy, a higher reliability can be achieved. Design examples are given to illustrate the key issues in single fault masking logic designs with error correcting codes. Reliabilities of different single fault masking carry lookahead adder designs are also examined

Online current testing

Testing professionals must choose the online VLSI testing technique most suitable for mission goals with respect to design complexity, fault coverage, safety level, and product value. Online current testing techniques provide potential solutions to reliability problems in a wide spectrum of fault-tolerant applications

Novel area-time efficient static CMOS totally self-checking comparator

The comparator is an essential element in concurrent error detection (CED). To ensure the correctness of error detection processes, comparators must be totally self-checking (TSC): any single fault occurring in the comparator must be detected by at least one normal input pattern, and before the detection of that fault, no erroneous output must be guaranteed. In this paper, an area-time efficient static CMOS TSC comparator design is presented. This comparator uses only eight transistors and is totally self-checking with respect to stuck-at faults, stuck-open, stuck-on, briding faults, and breaks

Analysis of a BICS-only concurrent error detection method

We propose in this paper a BICS-only method for concurrent error detection (CED) where a built-in current sensor (BICS) will be solely responsible for detecting faults and errors. Due to the wide applicability of the BICS, this approach can be applied directly to combinational circuits, sequential circuits, and even some analog circuits. A dependability model was developed to study the effectiveness of the proposed BICS-only method. The unsafe probability of the BICS-only design is sensitive to both fault coverage and testability of the BICS. When used in a duplicated CED system for fault masking, the system reliability is sensitive to the fault coverage, but not to the testability of the BICS. Next, we show that a dramatic increase in unsafe probability is possible if the BICS cannot make detection at every system clock cycle. A higher testability for BICS will, contrary to our intuition, make the unsafe probability higher. For duplicated CED applications, the reliability will be even lower than that of a nonredundant system. Therefore, the design criteria for BICS in the BICS-only method, in the order of importance, are: operating speed, fault coverage, and testability

Reliable Floating-Point Arithmetic Algorithms for Error-Coded Operands

Reliable floating-point arithmetic is vital for dependable computing systems. It is also important for future high-density VLSI realizations that are vulnerable to soft-errors. However, the direct checking of floating-point arithmetic is still an open problem. We present in this paper a set of reliable floating-point arithmetic algorithms for low-cost residue encoded and Berger encoded operands, respectively. Closed form equations are derived for floating-point addition, subtraction, multiplication, and division. Given the standard IEEE floating-point numbers, the proposed reliable floating-point multiplication algorithms for low-cost residue encoded operands are extremely low-cost: it requires less than 8% of hardware redundancy in all cases. For reliable floating-point addition and subtraction, we find the hardware redundancy ratios of applying low-cost residue code is about the same as that of applying Berger code: less than 40% of hardware redundancy for single precision numbers and about 16% for double precision numbers. For reliable floating-point division, Berger encoded operands yields hardware cost-effectiveness: about 45% for single precision numbers and about 36% for double precision numbers. © 1994 IEE

Fault-tolerant content addressable memory

In this paper, we analyze the error behavior of content addressable memories and provide necessary and sufficient conditions to protect them. Single error tolerant designs are demonstrated for bit- and byte-organized content addressable memories. This level of protection is equivalent to that of the conventional ECC protection in memory subsystems

Fault-tolerant associative approach to on-line memory repair

A fault-tolerant associative approach is proposed to be used in on-line repair for highly available memories. The memory repair mechanism is designed similar to a cache memory in its spare to main memory mapping schemes. Four spare memory mapping schemes are presented: fully associative, associative direct, associative set and associative multiple. If cache memory repair is needed, the proposed schemes can also be applied. The repair mechanism consists of a TMR content addressable memory (CAM) and an SEC/DED spare data memory. Although it is sufficient to encode the CAM with SEC code, we find that TMR version is faster in accessing time and more cost-effective. To repair a 1M×32 main memory with eight spare words, the proposed schemes use less than 0.015% of hardware redundanc

Highly reliable systems with differential built-in current sensors

A duplicated system with a differential built-in current sensor (DBICS) method is proposed in this paper as an alternative to the classical TMR designs. The DBICS compares the IDDQ levels of the two copies from a duplicated system and then selects the correct output. Unlike the previously known duplicated-with-self-checking scheme, the proposed method is easy to design and to implement. Further, the system block can be either combinational or sequential circuits and whose size is limited only by the capability of the BICS. The extremely low redundancy level of the proposed method, ≈1% or less, enables a very high reliability performance, more than any existing technique. As the failure rates of modern submicron and deep sub-micron VLSI chips are increasing, the proposed technique will allow the use of modern high-performance chips in highly critical applications