Algorithmic strategies for FPGA-based vision

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms, particularly on a stream processing mode. Case studies on FPGA implementations of standard corner detections (Harris, FAST and SUSAN) were carried out and analyzed to highlight the differences between hardware and software. Through this analysis, it was observed that an efficient software algorithm may not retain its speed advantage in the hardware domain. In fact, algorithms that are slower in software, can achieve comparable or faster performance in the hardware domain with the appropriate implementation compared to algorithms optimized for serial processing. Other observations include the optimization goals for FPGA implementation, the opportunities present in FPGAs that can be exploited, and properties of algorithms that are suitable and unsuitable for FPGA implementation. The outcome is a set of guidelines and principles for an FPGA-tailored algorithm. This information is then used in the design of a face detection algorithm optimized for FPGA implementation. This algorithm was deliberately designed to use operations suitable for FPGAs, based on the insights gained from the corner detection case studies. The result is a face detection algorithm that is unattractive as a software implementation, but is a reasonable choice as an FPGA implementation. The FPGA implementation of this algorithm achieves high theoretical framerates, and is implementable on a low-cost, low-end FPGA development board. This implementation is also competitive with FPGA implementations of the software-optimized Viola-Jones algorithm, especially on lower-end devices

Algorithmic strategies for FPGA-based vision

As demands for real-time computer vision applications increase, implementations on alternative architectures have been explored. These architectures include Field-Programmable Gate Arrays (FPGAs), which offer a high degree of flexibility and parallelism. A problem with this is that many computer vision algorithms have been optimized for serial processing, and this often does not map well to FPGA implementation. This thesis introduces the concept of FPGA-tailored computer vision algorithms, particularly on a stream processing mode. Case studies on FPGA implementations of standard corner detections (Harris, FAST and SUSAN) were carried out and analyzed to highlight the differences between hardware and software. Through this analysis, it was observed that an efficient software algorithm may not retain its speed advantage in the hardware domain. In fact, algorithms that are slower in software, can achieve comparable or faster performance in the hardware domain with the appropriate implementation compared to algorithms optimized for serial processing. Other observations include the optimization goals for FPGA implementation, the opportunities present in FPGAs that can be exploited, and properties of algorithms that are suitable and unsuitable for FPGA implementation. The outcome is a set of guidelines and principles for an FPGA-tailored algorithm. This information is then used in the design of a face detection algorithm optimized for FPGA implementation. This algorithm was deliberately designed to use operations suitable for FPGAs, based on the insights gained from the corner detection case studies. The result is a face detection algorithm that is unattractive as a software implementation, but is a reasonable choice as an FPGA implementation. The FPGA implementation of this algorithm achieves high theoretical framerates, and is implementable on a low-cost, low-end FPGA development board. This implementation is also competitive with FPGA implementations of the software-optimized Viola-Jones algorithm, especially on lower-end devices

VLSI implementation of full adder-subtractor design

Low power consumption and high performance in Very Large Scale Integration (VLSI) design are the major concerns in order to develop an efficient electronic devices. Addition is commonly used arithmetic operation in most electronic system which requires high performance and low power consumption of full adder circuit. This study aimed to design a low power and high performance full adder-subtractor by using Complementary Metal Oxide Semiconductor (CMOS) technology. Four design approaches of 4 bit Full Adder-Subtractor (FAS) static CMOS FAS with Pass Transistor Logic (PTL) XOR, static CMOS FAS with Transmission Gate (TG) XOR, PTL FAS and TG FAS circuit have been implemented in 90 mn CMOS technology using synopsys galaxy custom designer and compared in term of power consumption, power-delay product and area. PTL FAS able to reduce 27 .7% of overall transistor collllt compared to both conventional static CMOS approach. For the 4 bit FAS design, PTL logic approach able to reduce 37. 78% of area occupied and 27. 78% of transistor collllt compared to static CMOS approaches. TG FAS has the lowest power consumption with 112.81 µW followed by PTL FAS with 133.34 µW, less than both conventional static CMOS approach. Results show that the PTL and TG approaches offer a low area and power consumption with a high performance of full adder-subtractor design

Preparation and Preliminary Structure–Activity Relationship Studies of Schwarzinicine A Analogs as Vasorelaxant Agents

Schwarzinicines A–D, a series of alkaloids recently discovered from Ficus schwarzii, exhibit pronounced vasorelaxant activity in rat isolated aorta. Building on this finding, a concise synthesis of schwarzinicines A and B has been reported, allowing further investigations into their biological properties. Herein, a preliminary exploration of the chemical space surrounding the structure of schwarzinicine A (1) was carried out aiming to identify structural features that are essential for vasorelaxant activity. A total of 57 analogs were synthesized and tested for vasorelaxant activity in rat isolated aorta. Both efficacy (Emax) and potency (EC50) of these analogs were compared. In addition to identifying structural features that are required for activity or associated with potency enhancement effect, four analogs showed significant potency improvements of up to 40.2-fold when compared to 1. Molecular dynamics simulation of a tetrameric 44-bound transient receptor potential canonical-6 (TRPC6) protein indicated that 44 could potentially form important interactions with the residues Glu509, Asp530, Lys748, Arg758, and Tyr521. These results may serve as a foundation for guiding further structural optimization of the schwarzinicine A scaffold, aiming to discover even more potent analogs