Retina-Inspired Carbon Nitride-Based Photonic Synapses for Selective Detection of UV Light

Photonic synapses combine sensing and processing in a single device, so they are promising candidates to emulate visual perception of a biological retina. However, photonic synapses with wavelength selectivity, which is a key property for visual perception, have not been developed so far. Herein, organic photonic synapses that selectively detect UV rays and process various optical stimuli are presented. The photonic synapses use carbon nitride (C3N4) as an UV-responsive floating-gate layer in transistor geometry. C3N4 nanodots dominantly absorb UV light; this trait is the basis of UV selectivity in these photonic synapses. The presented devices consume only 18.06 fJ per synaptic event, which is comparable to the energy consumption of biological synapses. Furthermore, in situ modulation of exposure to UV light is demonstrated by integrating the devices with UV transmittance modulators. These smart systems can be further developed to combine detection and dose-calculation to determine how and when to decrease UV transmittance for preventive health care.

An 8 x 8 nRERL serial multiplier for ultra-low-power applications

An 8 x 8-b nRERL serial multiplier is implemented in a 0.6- m n-well 3-metal CMOS pro- cess. nRERL (nMOS Reversible Energy Recov ery Logic) is a new reversible adiabatic logic circuit, which can be operated at the leakage-current lev el for ultra- low-energy applications. Measurement results show ed that the nRERL serial multiplier consumed only 0.9 % of the energy dissipation of the static CMOS one at the operating frequency 100 kHz at 5V, where its adiabatic and leakage losses were about equal.The test chip was fabricated with the help of IDEC program of KAIST, Taejon, Korea. This paper was sup- ported by NON DIRECTED RESEARCH FUND, Korea Research Foundation,throught Inter-university Semicon- ductor Research Center, Seoul National University, Seoul, Korea, from 1996 to 1999

Enhancing the Power of Battery

Slides from a presentation on technological developments in lithium batteries and their potential commercial applications

nMOS Reversible Energy Recovery Logic for Ultra-Low-Energy Applications

We propose a new fully reversible adiabatic logic, nMOS reversible energy recovery logic (nRERL), which uses nMOS transistors only and a simpler 6-phase clocked power. Its area overhead and energy consumption are smaller, compared with the other fully adiabatic logics. We employed bootstrapped nMOS switches to simplify the nRERL circuits. With the simulation results for a full adder, we confirmed that the nRERL circuit consumed substantially less energy than the other adiabatic logic circuits at low-speed operation. We evaluated a test chip implemented with 0.8- m CMOS technology, which included a chain of nRERL inverters integrated with a clocked power generator. The nRERL inverter chain of 2400 stages consumed the minimum energy at dd = 3 5 V at 55 kHz, where the adiabatic and leakage losses are about equal, which is only 4.50% of the dissipated energy of its corresponding CMOS circuit at dd = 09 V. In conclusion, nRERL is more suitable than the other adiabatic logic circuits for the applications that do not require high performance but low energy consumption

Reversible Energy Recovery logic circuits and its 8-phase clocked power generator for ultra-low-power applications

We proposed Reversible Energy Recovery Logic (RERL) using an 8-phase clocking scheme, which is a dual-rail reversible adiabatic logic for ultra-low-energy applications. Because we eliminated non-adiabatic energy loss in RERL by using the concept of reversible logic, RERL has only adiabatic and leakage losses. In this paper we explain its operation and logic design and present its simulation and experimental results. We also present an energy-efficient 8-phase, clocked power generator that uses an off-chip inductor. With simulation results for the full adder, we confirmed that the RERL circuit consumed substantially less energy than other logic circuits at low-speed operation. We evaluated a test chip implemented with a 0.6-µm CMOS technology, which integrated a chain of inverters with a clocked power generator. In the experimental results, the RERL circuit consumed only 4.5% of the dissipated energy of a static CMOS circuit at an optimal operating speed of 40 kHz. In conclusion, RERL is suitable for the applications that do not require high performance but low-energy consumption because its energy consumption can be decreased to the minimum by reducing the operating frequency until adiabatic and leakage losses are equa

A 16-bit carry-lookahead adder using reversible energy recoverylogic for ultra-low-energy systems

In this paper, we describe an energy-efficient carrylookahead adder using reversible energy recovery logic (RERL), which is a new dual-rail reversible adiabatic logic. We also describe an eight-phase, clocked power generator that requires an off-chip inductor. For the energy-efficient design of reversible logic, we explain how to control the overhead of reversibility with a self-energy-recovery circuit. A test chip was implemented with a 0.8- m CMOS technology, which included two 16-bit carrylookahead adders to allow fair comparison: an RERL one and a static CMOS one. Experimental results showed that the RERL adder had substantial advantages in energy consumption over the static CMOS one at low operating frequencies. We also confirmed that we could minimize the energy consumption in the RERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal

Reduction in energy consumption by bootstrapped n MOS switches inreversible adiabatic CMOS circuits

For ultra-low-energy applications, hootstrapped reversible-energy-re cove^ logic (bRERL) is proposed, which is a reversible adiabatic CMOS logic and requires an 8-phase clock. In hRERL, each transmission gate was replaced by a bootstrapped nMOS switch in the logic functional blocks of tRERI,. Using SPICE simulations, it was confirmed that the bRERL circuit consumed less energy and occupied less area than the tRERL circuit. The authors integrated a hRERL inverter chain with its 8-phase, clocked power generator in a test chip, which was fabricated with 0 . 6 C~M OS technology. They also confirmed that they could minimise the energy consumption in the hRERL circuit by reducing the operating frequency until adiabatic and leakage losses were equal.This work was supported through the ISRC by KoEd Research Foundation and through SNU Nanoelectronics Institute by LG Semiconductor. The test chip was fabricated with the help of LG Semiconductor

Smart Heating and Cooling Heat Pump System by Standing Column Well and Cross-Mixing Balancing Well Heat Exchangers

Standing column well (SCW) geothermal heat exchanger permits a bleeding discharge of less than 20% in the event of a maximum load, which is an inappropriate method of using underground water. In this study, the existing operational method of two adjacent SCW geothermal heat exchangers, each with a single well, was modified. This technology aims to improve the coefficient of performance (COP) of the geothermal system by fundamentally preventing underground water discharge and maintaining a constant temperature of the underground heat exchanger. To curb the bleed water discharge, two balancing wells of cross-mixing methods were employed. The result of the cooling and heating operations with the existing SCW heat exchange system and the balancing well cross-combined heat exchange system showed that the measured COP increases by 23% and 12% during the cooling and heating operations, respectively. When operating with a balanced well cross-mixed heat exchange system, the initial temperature of the underground was constant with a small standard deviation of 0.08–0.12 °C