OLED Encapsulation by Room Temperature Plasma-Assisted ALD Al2O3 Films

Organic light emitting diodes (OLEDs, both small molecule and polymer LEDs) require excellent gas and moisture permeation barrier layers to increase their lifetime. The quality of the barrier layer is ultimately controlled by the presence of defects in the layer. Although a barrier layer may be intrinsically excellent (water vapor transmission rate, WVTR = 10-6 g·m-2·day-1) the protected device may fail in the presence of defects that lead to preferential diffusion pathways for H2O (e.g., defects caused by particles from the environment and/or production process). The state-of-the-art barrier coatings are micrometer-thick multi-layer structure, in which organic interlayers are alternated with inorganic barrier layers with the purpose of decoupling the above-mentioned defects. Recently, atomic layer deposition (ALD) has been successfully tested for the deposition of very thin (<50 nm) single layer permeation barriers on pristine polymer substrates [1,2], showing the potential of this highly uniform and conformal deposition technique in the field of moisture permeation barriers. In this contribution the encapsulation of OLEDs by plasma-assisted ALD of thin (20-40 nm) Al2O3 layers is addressed. The layers are synthesized at room temperature by sequentially exposing the substrate to Al(CH3)3 vapor and a remote inductively coupled O2 plasma in Oxford Instruments FlexALTM and OpALTM reactors. The intrinsic quality of the deposited ALD layers was determined by monitoring the oxidation of a Ca film encapsulated by the Al2O3 film: WVTR values as low as 2·10-6 g·m-2·day-1 have been measured. The potential of ALD layers in encapsulating OLEDs, and therefore in successfully covering the defects present on the device, has been investigated by means of electroluminescence measurements of polymer-LEDs (effective emitting area of 5.8 cm2). The black spot density and area growth were followed as a function of the time under standard conditions of 20°C and 50% relative humidity. Within a 500 h test ALD-encapsulated OLEDs show approximately half the black spot density compared to devices encapsulated by plasma deposited a-SiNx:H (300 nm thick). The black spot density is further reduced by combining the a-SiNx:H and ALD Al2O3 layers. These results point towards a very promising application of ALD Al2O3 layers in the field of OLED encapsulation and will be interpreted in terms of possible mechanisms related to film growth in multi-layer structures

Thin SIMOX SOI material for half-micron CMOS

\u3cp\u3eThe properties of half-micron CMOS devices fabricated on thin film SIMOX SOI with different material quality will be presented. The gate oxide quality, diode leakage current and breakdown voltage of transistors will be shown. The influence of LDD dope and TiSi\u3csub\u3e2\u3c/sub\u3esalicide on the parasitic bipolar transistor breakdown is presented. Temperature measurements on SOI and bulk transistors are presented which show an increased heating effect for thin film SOI transistors.\u3c/p\u3

Method of manufacturing a display device

ICs (20) are nearly separated from the semiconductor substrate (10) on/in which they are formed. Subsequently, the substrate is positioned upside down on a substrate (carrier) (3) which is provided with glue (21) at the location of a crystal. After attachment of the crystal to the carrier, the semiconductor substrate is removed and the crystal remains attached to the carrier e.g. at the crossing of rows and columns. The separate crystals may contain TFTs (simple AM addressing) but also more complicated electronics (address of pixel in memory+identification)

Method of manufacturing a display device

ICs (20) are nearly separated from the semiconductor substrate (10) on/in which they are formed. Subsequently, the substrate is positioned upside down on a substrate (carrier) (3) which is provided with glue (21) at the location of a crystal. After attachment of the crystal to the carrier, the semiconductor substrate is removed and the crystal remains attached to the carrier e.g. at the crossing of rows and columns. The separate crystals may contain TFTs (simple AM addressing) but also more complicated electronics (address of pixel in memory+identification)

Electronic device and method of manufacturing an electronic device

An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes

Electronic device and method of manufacturing an electronic device

An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes