A four-leg buck inverter for three-phase four-wire systems with the function of reducing DC-bus ripples

Three-phase four-wire inverters are usually used to feed unbalanced three-phase loads with neutral currents. The unbalanced three-phase loads also bring to second-order ripples in the DC bus, which should be mitigated by bulky DC-bus capacitors to improve the system performance. In this case, the DC capacitance is designed for the second-order ripple frequency instead of the switching frequency, so it can not be reduced even when SiC MOSFETs are adopted to achieve high switching frequency. Although various topologies of three-phase four-wire inverters has been proposed to provide the path for neutral currents, they cannot handle the second-order ripples. Also, some active power decoupling solutions can be adopted, but they require additional active swithes and components, which increases the cost of the system. In this paper, a four-leg buck inverter is proposed, which consists of four DC-DC buck converters. Each buck converter is independently controlled. This topology can not only provide neutral currents, but also reduce the second-order ripples in the DC bus with active power decoupling control. The proposed topology doesn't require any additional active switches comparing to the conventional topologies with neutral legs. The effectiveness of proposed topology is verified by the simulation in MATLAB/Simulink

A model-based DC fault location scheme for multi-terminal MMC-HVDC systems using a simplified transmission line representation

Accurately determining the location of DC pole-to-pole short-circuit faults in modular multilevel converter (MMC) based multi-terminal HVDC (MTDC) systems is key issue in ensuring fast power recovery. This paper proposes an effective DC fault location scheme for the MMC-MTDC that uses an estimated R-L representation of the transmission lines. By using the measured voltage and current data from both ends of the faulted DC line, the proposed fault location formulas can calculate the location of the fault with high accuracy. The simplified R-L representation greatly reduces the computation burden of the fault detection algorithm. Electromagnetic transient (EMT) simulations of a four-terminal MMC-MTDC system on PSCAD/EMTDC are used to confirm the effectiveness of the proposed approach. The results verify that the proposed scheme is robust and almost not affected by the transmitted power or the fault resistance

A SiC-based neutral leg for the three-phase four-wire inverter

SiC-based inverters can operate at high switching frequency with high efficiency, which can reduce the size of passive components and heat sinks to achieve high power density. However, in three-phase four-wire inverters supplying unblanced loads, the second-order ripples in the DC bus need to be mitigated by large DC capacitance, which increases the size of the converter. The conventional neutral leg is widely used in three-phase four-wire inverters to provide neutral currents for the unbalanced loads. In this paper, an improved neutral leg is proposed, which can provide neutral currents and reduce the second-order ripples in the DC bus simultaneously. The DC bus ripples can be reduced without adding any hardware components. Furthermore, the proposed neutral leg can save 50% DC capacitance comparing to the conventional neutral leg. The proposed neutral leg was built with SiC MOSFETs and tested with a three-phase four-wire inverter in the laboratory. The experimental results verified the effectiveness of the proposed neutral leg

Reduction of DC-link ripples for SiC-based three-phase four-wire inverters with unbalanced loads

Three-phase inverters are widely used in the smart grid to integrate renewable energy resources. When the inverters are used to feed the unbalanced three-phase loads, the threephase four-wire inverters are usually required to provide the current path for neutral currents. However, unbalanced loads will cause undesirable second-order ripples on DC bus. Conventional three-phase four-wire inverters with neutral legs can not address this challenge. Bulky capacitors or extra active circuits are still required to reduce the ripples. This inevitably leads to increased size and cost of the system. Although SiC-based converters have the advantage of achieving high power density, the DCbus capacitance can not be reduced by simply replacing Si IGBTs with SiC MOSFETs. In this paper, a new topology of SiC-based three-phase four-wire inverters is proposed to reduce the DC-bus ripples without adding any additional hardware components. With the reduction of DC-bus ripples, the DC-bus capacitance can be reduced to achieve high power density. The equivalent circuit is analyzed and the control strategy for the proposed topology is designed. The proposed topology is built in Matlab/Simulink and simulation results are presented to verify the proposed topology

A multi-port current-limiting hybrid DC crcuit breaker

Recently the hybrid multi-port DC circuit breaker (MP-DCCB) is becoming popular in protecting HVDC grids, thanks to their re-duction of power electronics devices. In this paper, an enhanced multi-port current-limiting DCCB (MP-CLCB) for multiple line protection is proposed. The integrated fault current limiter (FCL) inside the MP-CLCB can clear the fault faster with slightly in-creased costs. To reduce the energy dissipation requirement for the surge arresters caused by the newly added current-limiting path, an energy transfer path which provides a loop with the in-ductors during the current decay stage is designed. The theoreti-cal analysis of the pre-charging, current-limiting, fault interrup-tion and energy dissipation of the MP-CLCB is carried out. Moreover, the design principles of the energy dissipation and the key parameters of the MP-CLCB are provided. The proposed approaches are verified through simulations in PSCAD/EMTDC. The results show that the MP-CLCB can replace multiple DCCBs, accelerate the fault current interruption and reduce the energy dissipation requirement for the surge arresters

Spatial targeting of type II protein kinase A to filopodia mediates the regulation of growth cone guidance by cAMP

The second messenger cyclic adenosine monophosphate (cAMP) plays a pivotal role in axonal growth and guidance, but its downstream mechanisms remain elusive. In this study, we report that type II protein kinase A (PKA) is highly enriched in growth cone filopodia, and this spatial localization enables the coupling of cAMP signaling to its specific effectors to regulate guidance responses. Disrupting the localization of PKA to filopodia impairs cAMP-mediated growth cone attraction and prevents the switching of repulsive responses to attraction by elevated cAMP. Our data further show that PKA targets protein phosphatase-1 (PP1) through the phosphorylation of a regulatory protein inhibitor-1 (I-1) to promote growth cone attraction. Finally, we find that I-1 and PP1 mediate growth cone repulsion induced by myelin-associated glycoprotein. These findings demonstrate that the spatial localization of type II PKA to growth cone filopodia plays an important role in the regulation of growth cone motility and guidance by cAMP

Dual harmonic injection for reducing the sub-module capacitor voltage ripples of hybrid MMC

Reducing the capacitor voltage ripples of the half-bridge sub-modules (HBSM) and full-bridge sub-modules (FBSM) in a hybrid modular multilevel converter (MMC) is expected to reduce the capacitance, volume and costs. To address this issue, this paper proposes a dual harmonic injection method which injects the second harmonic circulating current and third order harmonic voltage into the conventional MMC control. Firstly, the mathematical model of the proposed control is established and analyzed. Then, the general strategy of determining the amplitude and phase angle of each injection component is proposed to suppress the fluctuations of the fundamental and double frequency instantaneous power. The proposed strategy can achieve the optimal power fluctuation suppression under various operating conditions, which also has the advantage of reducing the voltage fluctuation difference between HB and FB SMs. The correctness and effectiveness of the proposed strategy are verified in simulations in PSCAD/EMTDC

Coordinated control of DC circuit breakers in multilink HVDC grid

High voltage DC grid is developing towards more terminals and larger transmission capacity, thus the requirements for DC circuit breakers (DCCB) will rise. The conventional methods only use the faulty line DCCB to withstand the fault stress, while this paper presents a coordination method of multiple DCCBs to protect the system. As many adjacent DCCBs are tripped to interrupt the fault current, the fault energy is shared, and the requirement for the faulty line DCCB is reduced. Moreover, the adjacent DCCBs are actively controlled to help system recovery. The primary protection, backup protection, and reclosing logic of multiple DCCB are studied. Simulation confirms that the proposed control reduces the energy dissipation requirement of faulty line DCCB by around 30–42 %, the required current rating for IGBTs is reduced, and the system recovery time reduced by 20–40 ms

A thyristor based DC fault current limiter with inductor inserting-bypassing capability

DC fault current limiters (FCL) are becoming increasingly important for the prompt DC fault clearance of modular multilevel converter (MMC) based HVDC grid. This paper proposes a hybrid FCL topology, in which the main current limiting circuit is composed of thyristors, capacitors and an inductor. Detailed theoretical analysis of the current limiting processes was carried out to check the electrical stresses. The relationship between the voltage stress and the current limiting time was analyzed, then a design method for the FCL parameters was provided. An effective method for fast bypassing the FCL inductor was proposed to reduce the energy dissipation when fault current is interrupted by a DC Circuit Breaker (DCCB). The dynamic performance of the proposed approach has shown that the proposed FCL can effectively limit the rate of rising of the DC fault current and reduce the energy dissipation