Active inductor shunt peaking in high-speed VCSEL driver design

An all transistor active inductor shunt peaking structure has been used in a prototype of 8-Gbps high-speed VCSEL driver which is designed for the optical link in ATLAS liquid Argon calorimeter upgrade. The VCSEL driver is fabricated in a commercial 0.25-um Silicon-on-Sapphire (SoS) CMOS process for radiation tolerant purpose. The all transistor active inductor shunt peaking is used to overcome the bandwidth limitation from the CMOS process. The peaking structure has the same peaking effect as the passive one, but takes a small area, does not need linear resistors and can overcome the process variation by adjust the peaking strength via an external control. The design has been tapped out, and the prototype has been proofed by the preliminary electrical test results and bit error ratio test results. The driver achieves 8-Gbps data rate as simulated with the peaking. We present the all transistor active inductor shunt peaking structure, simulation and test results in this paper.Comment: 4 pages, 6 figures and 1 table, Submitted to 'Chinese Physics C

Demonstration of Adiabatic Variational Quantum Computing with a Superconducting Quantum Coprocessor

Adiabatic quantum computing enables the preparation of many-body ground states. This is key for applications in chemistry, materials science, and beyond. Realisation poses major experimental challenges: Direct analog implementation requires complex Hamiltonian engineering, while the digitised version needs deep quantum gate circuits. To bypass these obstacles, we suggest an adiabatic variational hybrid algorithm, which employs short quantum circuits and provides a systematic quantum adiabatic optimisation of the circuit parameters. The quantum adiabatic theorem promises not only the ground state but also that the excited eigenstates can be found. We report the first experimental demonstration that many-body eigenstates can be efficiently prepared by an adiabatic variational algorithm assisted with a multi-qubit superconducting coprocessor. We track the real-time evolution of the ground and exited states of transverse-field Ising spins with a fidelity up that can reach about 99%.Comment: 12 pages, 4 figure

Experimental Simulation of Larger Quantum Circuits with Fewer Superconducting Qubits

Although near-term quantum computing devices are still limited by the quantity and quality of qubits in the so-called NISQ era, quantum computational advantage has been experimentally demonstrated. Moreover, hybrid architectures of quantum and classical computing have become the main paradigm for exhibiting NISQ applications, where low-depth quantum circuits are repeatedly applied. In order to further scale up the problem size solvable by the NISQ devices, it is also possible to reduce the number of physical qubits by "cutting" the quantum circuit into different pieces. In this work, we experimentally demonstrated a circuit-cutting method for simulating quantum circuits involving many logical qubits, using only a few physical superconducting qubits. By exploiting the symmetry of linear-cluster states, we can estimate the effectiveness of circuit-cutting for simulating up to 33-qubit linear-cluster states, using at most 4 physical qubits for each subcircuit. Specifically, for the 12-qubit linear-cluster state, we found that the experimental fidelity bound can reach as much as 0.734, which is about 19\% higher than a direct simulation {on the same} 12-qubit superconducting processor. Our results indicate that circuit-cutting represents a feasible approach of simulating quantum circuits using much fewer qubits, while achieving a much higher circuit fidelity