3 research outputs found
SynFull-RTL: evaluation methodology for RTL NoC designs
SynFull is a widely employed tool that generates realistic traffic patterns for the performance evaluation of a NoC. In this work, we identify the main limitations of SynFull: high variability and long simulation time and also that these limitations increase when SynFull is integrated with RTL designs. SynFull-RTL employs a statistical approach, simulating each application macro-phase only once and averaging according to its probability of occurrence and the measured traffic load. SynFull-RTL obtains higher accuracy than the original version and reduced variability, with observed 40Ă reduction in simulation time and resources. A use-case with ProSMART validates the results.This work has been supported by the Spanish Science and Technology Commission under contract PID2019-105660RB-C22 and the European HiPEAC Network of Excellence. Enrique Vallejo has been partially supported by the Ministry of Universities, Subprograma Estatal de Movilidad, grant number PRX21/00757. This work also received funding from the European Union Horizon 2020 research and innovation programme under grant agreements number 826647 (EPI) and 946002 (MEEP).Peer ReviewedPostprint (author's final draft
Sargantana: A 1 GHz+ in-order RISC-V processor with SIMD vector extensions in 22nm FD-SOI
The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA. In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom application-specific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sar-gantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology. As a result, Sargantana delivers a 1.77Ă higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-of-the-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrial-class performance requirements for scientific, real-time, and high-performance computing applications.This work has been partially supported by the Spanish Ministry of Economy and Competitiveness (contract PID2019- 107255GB-C21), by the Generalitat de Catalunya (contract 2017-SGR-1328), by the European Union within the framework of the ERDF of Catalonia 2014-2020 under the DRAC project [001-P-001723], and by Lenovo-BSC Contract-Framework (2020). The Spanish Ministry of Economy, Industry and Competitiveness has partially supported M. Doblas and V. Soria-Pardos through a FPU fellowship no. FPU20-04076 and FPU20-02132 respectively. G. Lopez-Paradis has been supported by the Generalitat de Catalunya through a FI fellowship 2021FI-B00994. S. Marco-Sola was supported by Juan de la Cierva fellowship grant IJC2020-045916-I funded by MCIN/AEI/10.13039/501100011033 and by âEuropean Union NextGenerationEU/PRTRâ, and M. MoretĂł through a Ramon y Cajal fellowship no. RYC-2016-21104.Peer ReviewedPostprint (author's final draft
DVINO: A RISC-V vector processor implemented in 65nm technology
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedArticle signat per 43 autors/es: Guillem Caboâ, Gerard CandĂłnâ, Xavier Carrilâ, Max Doblasâ, Marc DomĂnguezâ, Alberto GonzĂĄlezâ, Cesar HernĂĄndezâ , VĂctor JimĂ©nezâ, Vatistas Kostalamprosâ, RubĂ©n Langaritaâ, Neiel Leyvaâ , Guillem LĂłpez-ParadĂsâ, Jonnatan Mendozaâ, Francesco Minerviniâ, Julian PavĂłnâ, Cristobal RamĂrezâ, NarcĂs Rodasâ, Enrico Reggianiâ, Mario RodrĂguezâ, Carlos Rojasâ, Abraham Ruizâ, VĂctor Soriaâ, Alejandro SuanesâĄ, IvĂĄn Vargasâ, Roger Figuerasâ, Pau Fontovaâ, Joan Marimonâ, VĂctor Montabesâ, AdriĂĄn Cristalâ, Carles HernĂĄndezâ, Ricardo MartĂnezâĄ, Miquel MoretĂłâ§, Francesc Mollâ§, Oscar Palomarâ§, Marco A. RamĂrezâ , Antonio Rubio§, Jordi SacristĂĄnâĄ, Francesc Serra-GraellsâĄ, Nehir Sonmezâ, LluĂs TerĂ©sâĄ, Osman Unsalâ, Mateo Valeroâ§, LuĂs Villaâ // âBarcelona Supercomputing Center (BSC), Barcelona, Spain. Email: [email protected]; â Centro de InvestigaciĂłn en ComputaciĂłn, Instituto PolitĂ©cnico Nacional (CIC-IPN), Mexico City, Mexico; ⥠Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: [email protected]; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: [email protected] (author's final draft