Life cycle cost modeling of automotive paint systems

Thesis (M.B.A.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science; in conjunction with the Leaders for Manufacturing Program at MIT, 2007.Includes bibliographical references (p. 88-89).Vehicle coating is an important component of automotive manufacturing. The paint shop constitutes the plurality of initial investment in an automotive assembly plant, consumes the majority of energy used in the plant's operation, and generates significant waste from paint overspray. The coating process also results in the emission of polluting volatile organic compounds (VOCs). New paint technologies based upon powder coatings offer reductions in VOC emissions along with potentially reduced energy usage and the ability to reuse paint overspray. However, quantification of these advantages requires clear understanding of the life cycle costs associated with each paint technology, modeled over the decades-long time horizons within which a paint shop operates. Life cycle cost models go beyond acquisition cost to consider all relevant cost drivers for a given system. This includes obvious candidates such as investment and operating costs, but also may include more subtle factors such as costs associated with variation, disruption, or flexibility, hereafter referred to as hidden costs.(cont.) In this thesis, methods for estimating these costs for a paint shop are explored. First, the development of a life cycle cost modeling tool, capable of quickly forecasting investment and operating costs and testing the sensitivity of life cycle cost to changes in input costs, is discussed. This tool is then used to compare the life cycle cost of three different primer surfacer application technologies. Next, the potential impact of hidden costs on life cycle cost for manufacturing systems are investigated, both through real-world examples and simulations. Finally, this thesis explores the wider implications of a shift to life cycle cost analysis for General Motors, in terms of both internal and external relationships for the Global Paint and Polymers Center at General Motors, and identifies situations in which a focus on life cycle cost can bolster managerial objectives.by Christopher W. Leitz.S.M.M.B.A

High hole and electron mobilities using Strained Si/Strained Ge heterostructures

PMOS and NMOS mobility characteristics of the dual channel (strained Si/strained Ge) heterostructure have been reviewed. It is shown that the dual channel heterostructure can provide substantially enhanced mobilities for both electrons and holes. However, germanium interdiffusion from the germanium rich buried layer into the underlying buffer layer could potentially reduce the hole mobility enhancements.Singapore-MIT Alliance (SMA

MOSFET Channel Engineering using Strained Si, SiGe, and Ge Channels

Biaxial tensile strained Si grown on SiGe virtual substrates will be incorporated into future generations of CMOS technology due to the lack of performance increase with scaling. Compressively strained Ge-rich alloys with high hole mobilities can also be grown on relaxed SiGe. We review progress in strained Si and dual channel heterostructures, and also introduce high hole mobility digital alloy heterostructures. By optimizing growth conditions and understanding the physics of hole and electron transport in these devices, we have fabricated nearly symmetric mobility p- and n-MOSFETs on a common Si₀.₅Ge₀.₅ virtual substrate.Singapore-MIT Alliance (SMA

SiGeC Near Infrared Photodetectors

A near infrared waveguide photodetector in Si-based ternary Si₁âxâyGexCy alloy was demonstrated for 0.85~1.06 µm wavelength fiber-optic interconnection system applications. Two sets of detectors with active absorption layer compositions of Si₀.₇₉Ge₀.₂C₀.₀₁ and Si₀.₇₀Ge₀.₂₈C₀.₀₂ were designed. The active absorption layer has a thickness of 120~450 nm. The external quantum efficiency can reach ~3% with a cut-off wavelength of around 1.2 µm.Singapore-MIT Alliance (SMA

Strained Ge channel p-type metal-oxide-semiconductor field-effect transistors grown on SiââxGex/Si virtual substrates

We have fabricated strained Ge channel p-type metal-oxide-semiconductor field-effect transistors (p-MOSFETs) on Siâ.âGeâ.â virtual substrates. The poor interface between silicon dioxide (SiOâ) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400° C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly 8 times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm²/V-s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement mode MOSFET with buried channel-like transport characteristics.Singapore-MIT Alliance (SMA

Si Industry at a Crossroads: New Materials or New Factories?

Many trends in the silicon industry could be interpreted as the herald of the end of traditional Si scaling. If this premise holds, future performance and system-on-chip applications may not be reached with conventional Si technology extensions. We review progress towards our vision that a larger crystal structure on Si, namely relaxed SiGe epitaxial layers, can support many generations of higher performance Si CMOS and new system-on-chip functionality without the expense of significant new equipment and change to CMOS manufacturing ideology. We will review the impact of tensile strained Si layers grown on relaxed SiGe layers. Both NMOS and PMOS exhibit higher carrier mobilities due to the strained Si MOSFET channel. Heterostructure MOSFETs designed on relaxed SiGe can have multiple-generation performance increases, and therefore determine a new performance roadmap for Si CMOS technology, independent of MOSFET gate length. We also indicate that this materials platform naturally leads to incorporating new optical functionality into Si CMOS technology.Singapore-MIT Alliance (SMA

Single electron Sensitive Readout (SiSeRO) X-ray detectors: Technological progress and characterization

Single electron Sensitive Read Out (SiSeRO) is a novel on-chip charge detector output stage for charge-coupled device (CCD) image sensors. Developed at MIT Lincoln Laboratory, this technology uses a p-MOSFET transistor with a depleted internal gate beneath the transistor channel. The transistor source-drain current is modulated by the transfer of charge into the internal gate. At Stanford, we have developed a readout module based on the drain current of the on-chip transistor to characterize the device. Characterization was performed for a number of prototype sensors with different device architectures, e.g. location of the internal gate, MOSFET polysilicon gate structure, and location of the trough in the internal gate with respect to the source and drain of the MOSFET (the trough is introduced to confine the charge in the internal gate). Using a buried-channel SiSeRO, we have achieved a charge/current conversion gain of >700 pA per electron, an equivalent noise charge (ENC) of around 6 electrons root mean square (RMS), and a full width half maximum (FWHM) of approximately 140 eV at 5.9 keV at a readout speed of 625 Kpixel/s. In this paper, we discuss the SiSeRO working principle, the readout module developed at Stanford, and the characterization test results of the SiSeRO prototypes. We also discuss the potential to implement Repetitive Non-Destructive Readout (RNDR) with these devices and the preliminary results which can in principle yield sub-electron ENC performance. Additional measurements and detailed device simulations will be essential to mature the SiSeRO technology. However, this new device class presents an exciting technology for next generation astronomical X-ray telescopes requiring fast, low-noise, radiation hard megapixel imagers with moderate spectroscopic resolution.Comment: To appear in SPIE Proceedings of Astronomical Telescopes + Instrumentation, 202

The high-speed X-ray camera on AXIS

AXIS is a Probe-class mission concept that will provide high-throughput, high-spatial-resolution X-ray spectral imaging, enabling transformative studies of high-energy astrophysical phenomena. To take advantage of the advanced optics and avoid photon pile-up, the AXIS focal plane requires detectors with readout rates at least 20 times faster than previous soft X-ray imaging spectrometers flying aboard missions such as Chandra and Suzaku, while retaining the low noise, excellent spectral performance, and low power requirements of those instruments. We present the design of the AXIS high-speed X-ray camera, which baselines large-format MIT Lincoln Laboratory CCDs employing low-noise pJFET output amplifiers and a single-layer polysilicon gate structure that allows fast, low-power clocking. These detectors are combined with an integrated high-speed, low-noise ASIC readout chip from Stanford University that provides better performance than conventional discrete solutions at a fraction of their power consumption and footprint. Our complementary front-end electronics concept employs state of the art digital video waveform capture and advanced signal processing to deliver low noise at high speed. We review the current performance of this technology, highlighting recent improvements on prototype devices that achieve excellent noise characteristics at the required readout rate. We present measurements of the CCD spectral response across the AXIS energy band, augmenting lab measurements with detector simulations that help us understand sources of charge loss and evaluate the quality of the CCD backside passivation technique. We show that our technology is on a path that will meet our requirements and enable AXIS to achieve world-class science.Comment: 17 pages, 11 figures, submitted to Proceedings of SPIE Optics + Photonics 202

High mobility strained Si/SiGe heterostructure MOSFETs : channel engineering and virtual substrate optimization

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2002.Includes bibliographical references (leaves 163-174).High quality relaxed silicon-germanium graded buffers are an important platform for monolithic integration of high speed heterostructure field-effect transistors and III-V-based optoelectronics onto silicon substrates. In this thesis, dislocation dynamics in compositionally graded SiGe layers are explored and mobility enhancements in strained Si/SiGe metal-oxide-semiconductor field-effect transistors (MOSFETs) are evaluated. These results demonstrate the dramatic increases in microelectronics performance and functionality that can be obtained through use of the relaxed SiGe integration platform. By extending and modifying a model for dislocation glide kinetics in graded buffers to SiGe/Si, a complete picture of strain relaxation in SiGe graded buffers emerges. To investigate dislocation glide kinetics in these structures, a series of identical samples graded to 30% Ge have been grown at temperatures between 650ʻC and 900ʻC on (001)-, (001) offcut 6ʻ towards an in-plane -, and (001) offcut 6ʻ towards an in-plane -oriented Si substrates. The evolution of field threading dislocation density (TDD) with growth temperature in the on-axis samples indicates that dislocation nucleation and glide kinetics together control dislocation density in graded buffers. The TDD of samples grown on offcut substrates exhibits a more complicated temperature dependence, due to their reduced tendency towards dislocation pile-up formation at low temperature and dislocation reduction reactions at high temperature. Finally, by evaluating field threading dislocation density and dislocation pile-up density in a wide variety of SiGe graded buffers, a correlation between dislocation pile-up formation and increases in field threading dislocation density emerges.(cont.) Record mobility strained Si p-MOSFETs have been fabricated on relaxed 40% Ge virtual substrates. Hole mobility enhancements saturate at virtual substrate compositions of 40% Ge and above, with mobility enhancements over twice that of co-processed bulk Si devices. In contrast, hole mobility in strained Si p-MOSFETs displays no strong dependence on strained layer thickness. These results indicate that strain is the primary variable in determining hole mobility in strained Si p-MOSFETs and that symmetric electron and hole mobility enhancements in strained Si MOSFETs can be obtained for virtual substrate compositions beyond 35% Ge. The effect of alloy scattering on carrier mobility in tensile strained SiGe surface channel MOSFETs is measured directly for the first time. Electron mobility is degraded much more severely than hole mobility in these heterostructures, in agreement with theoretical predictions. Dual channel heterostructures, which consist of the combination of buried compressively strained SiilyGey buried channels and tensile strained Si surface channels, grown on relaxed SilxGex virtual substrates, are explored in detail for the first time. Hole mobilities exceeding 700 cm2/V-s have been achieved by combining tensile strained Si surface channels and compressively strained 80% Ge buried channels grown on relaxed 50% Ge virtual substrates. This layer sequence exhibits nearly symmetric electron and hole mobilities, both enhanced relative to bulk Si ...by Christopher W. Leitz.Ph.D

Novel CMOS-Compatible Optical Platform

A research synopsis is presented summarizing work with integration of Ge and III-V semiconductors and optical devices with Si. III-V GaAs/AlGaAs quantum well lasers and GaAs/AlGaAs optical circuit structures have been fabricated on Si using Ge/GeSi/Si virtual substrates. The lasers fabricated on bulk GaAs showed similar output characteristics as those on Si. The GaAs/AlGaAs lasers fabricated on Si emitted at 858nm and had room temperature cw lifetimes of ~4hours. Straight optical links integrating an LED emitter, waveguide and detector exhibited losses of approximately 144dB/cm. A process for fabrication of a novel CMOS-compatible platform that integrates III-V or Ge layers with Si is demonstrated. Thin Ge layers have been transferred from Ge/GeSi/Si virtual substrates to bulk Si utilizing wafer bonding and an epitaxial Si CMP layer to facilitate virtual substrate planarization. A unique CMP-less method for removal of Ge exfoliation damage induced by the SmartCut⢠process is also presented.Singapore-MIT Alliance (SMA