Chaotic behavior in super regenerative detectors

In this paper the super regenerative detector, as proposed by Armstrong in 1922, is investigated. We show that in a simplified model the current in the circuit behaves chaotically during a small period in time after which the circuit becomes an oscillator. Armstrong was not aware of the circuits' chaotic behavior, but reported strange irregular start-ups of the oscillator. Chaotic behavior of the circuit is demonstrated in this paper using computer simulation. During the period in which the irregularities appear, the amplification of the circuit is maxima

Ultra wide band (UWB) technology

\u3cp\u3eShort-range communication systems (known as wireless personal area network [WPAN] systems) with ranges of up to 10 m are becoming popular for replacing cables and enabling new consumer applications. However, systems such as Bluetooth and Zigbee, which operate in the 2.4 GHz ISM band, have a limited data rate, typically about 1 Mbps, which is insufficient for many applications, such as fast transfer of large files (e.g., wireless USB) and high-quality video streaming. To increase the data rate to several hundreds of Mbps, a higher bandwidth is preferred over a larger signal-to-noise ratio (SNR). This became possible when the FCC released frequency spectrum for ultra wide band (UWB) in the United States spanning from 3.1 to 10.6 GHz with an average transmit power level of only -41.3 dBm/MHz [1]. Since then, several proposals have been presented to realize a shortrange high data rate communication link. At present, both direct-sequence impulse communication and multiband orthogonal frequency division multiplexing (MB-OFDM) UWB systems are under consideration as a standard within the IEEE under IEEE802.15.3a. Industry has adopted MBOFDM UWB for high data rates as the ECMA-368 standard [2].\u3c/p\u3

Wireless infrastructure

\u3cp\u3eThe recent and dramatic increase in demand for mobile data communication, driven by consumer devices such as smartphones and tablets, is resulting in heightened technical challenges for the wireless infrastructure that lies as a bridge in-between these mobile terminals and the wired network transferring the data between final users. Several challenges arise in the design of the electronics behind the wireless infrastructure access points, or base-stations. This Chapter provides an overview of the present state, challenges and trends in the RF, analog and mixed signal electronics for wireless infrastructure and provides a frame to orient the reader of this book to the following chapters covering the specifics of the technologies involved. © 2013\u3c/p\u3

Estimation of the basin of attractions of stable equilibrium points in CNNs

We present an approach to estimate the basin of attraction of stable equilibrium points in cellular neural networks (CNNs). The approach is based on the determination of the so called tree of regions connected with each stable equilibrium points described in our previous work (1997). The new contribution is connected with additional separation of the regions where the boundaries between different basins are located. The suggested separation with internal hyperplanes will help to estimate more precisely the boundaries between different basins, because the previous algorithm to obtain the trees could not give the exact description of the basin of attractions

Infulence of substrate noise on RF performance

A low-ohmic substrate 0.25µm CMOS process has been chosen to carry out experiments to measure the effects of substrate noise on the performance of circuits operating at radio frequencies. Clock circuits give rise to substrate noise with spectral harmonics far into the RF band. These harmonics are injected into the signal path of RF circuitry as will be demonstrated. Clock planning is therefore a major issue in mixed-signal telecommunication

Explicit formulas for the solutions of piecewise linear networks

A methodology is presented for obtaining explicit formulas for the solution of class-P piecewise linear (PL) networks and, inherently, for the linear complementary problem (LCP). The method uses the [.] operator, which has been previously defined in the literature to extend the explicit PL model descriptions of Chua. An important consequence of the methodology is that it proves that class-P networks have explicit solution

CMOS switched current phase-locked loop

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consume

A novel compact architecture for a programmable full-range CNN in 0,5µm CMOS technology

Describes an analogue hardware implementation of a programmable full-range CNN. The used technology is the MIETEC 0.5 /spl mu/m CMOS process. The most important building blocks in each cell are its multipliers and an integrator with a hard-limited output. For the multipliers it is shown that the application of 2-quadrant types suffices, without loss of generality of the resulting network. As the number of multipliers per cell can be quite large, this means an important reduction of the circuit complexity. The integrator is implemented as a single capacitor. Hard-limiting is incorporated by a small clamper circuit. The resulting low-power and low-voltage circuit stands out for its low number of components and dense implementation. Its usefulness is illustrated with simulation results of this CNN used as a connected component detector

A 58-64 GHz transformer-based differential rectifier in 40 nm CMOS with -12 dBm sensitivity for 1 V at 64 GHz

This paper presents a 60 GHz band transformer-based inductor peaked differential rectifier in a 40 nm CMOS technology. The rectifier is used as a wireless power receiver in a monolithic wireless powered IoT transponder. A new transformer-based inductor peaked differential topology is proposed and implemented to improve the sensitivity. In this method, the input transformer performs voltage boosting function, inductor peaking function, and impedance transfer function simultaneously within a compact die size. The proposed rectifier topology achieves an excellent peak sensitivity of -12 dBm at 64 GHz for 1 V output voltage. The overall sensitivity over the entire operational range of 58-64 GHz is below - 5 dBm

Silicon-based true-time-delay phased-array front-ends at ka-band

\u3cp\u3eA high-power and a low-power fully integrated true-time-delay (TTD) phased-array receiver front-end have been developed for Ka-band applications using a 0.25-μm SiGe:C BiCMOS technology. The high-power front-end, consisting of a high-power low-noise amplifier (LNA) and an active TTD phase shifter, achieves 13.8 ±1.3 dB gain and a noise figure (NF) below 3.1 dB at 30 GHz. The front-end provides 17.8-ps continuous variable delay, with 3.5% normalized delay variation (NDV) over a 22-37-GHz frequency span. The low-power front-end, composed of a low-power LNA and a passive TTD phase shifter, achieves 14.8±3dB gain and an NF below 3.2 dB at 30 GHz. The low-power front-end offers 22-ps continuous variable delay with only 5.5% NDV over a 24-40-GHz frequency span. The low-power front-end consumes 22.5-mW power and presents an overall input 1-dB compression point (P\u3csub\u3e1 dB\u3c/sub\u3e) and input third-order intercept point (IIP3) of-22 and-13.8 dBm, respectively. Depending on the linearity requirements, the high-power front-end can operate in dual-power modes. In the high-power (low-power) mode, the measured worst case input P\u3csub\u3e1 dB\u3c/sub\u3e and IIP3 are-15.8 (-18 dBm) and-9 dBm (-12 dBm) at 30 GHz with an averaged power consumption per channel of 269 mW (111 mW) for similar TTD and gain performance. The core area of the high-power and low-power front-ends are 0.31 and 0.48 mm}}\u3csup\u3e2\u3c/sup\u3e, respectively.\u3c/p\u3