2 research outputs found
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
Abstract—This paper concerns automatic hardware synthesis
from data flow graph (DFG) specification in system level design. In
the presented design methodology, each node of a data flow graph
represents a hardware library module that contains a synthesizable
VHDL code. Our proposed technique automatically synthesizes a
clever control structure, cascaded counter controller, that supports
asynchronous interaction with outside modules while efficiently
implementing the synchronous dataflow semantics of the graph
at the same time. Through comparison with previous works with
some examples, the novelty of the proposed technique is demonstrated.This work
was supported by the National Research Laboratory (NRL) Grant and the Brain
Korea 21 Project. The RIACT at Seoul National University provides research
facilities for this study
Efficient Hardware Controller Synthesis for Synchronous Dataflow Graph in System Level Design
This paper concerns automatic hardware synthesis from data flow graph (DFG) specification in system level design. In the presented design methodology, each node of a data flow graph represents a hardware library module that contains a synthesizable VHDL code. Our proposed technique automatically synthesizes a clever control structure, cascaded counter controller, that supports asynchronous interaction with outside modules while efficiently implementing the synchronous dataflow semantics of the graph at the same time. Through comparison with previous work with some examples, the novelty of the proposed technique is demonstrated