BackTrack: Robust template update via Backward Tracking of candidate template

Variations of target appearance such as deformations, illumination variance, occlusion, etc., are the major challenges of visual object tracking that negatively impact the performance of a tracker. An effective method to tackle these challenges is template update, which updates the template to reflect the change of appearance in the target object during tracking. However, with template updates, inadequate quality of new templates or inappropriate timing of updates may induce a model drift problem, which severely degrades the tracking performance. Here, we propose BackTrack, a robust and reliable method to quantify the confidence of the candidate template by backward tracking it on the past frames. Based on the confidence score of candidates from BackTrack, we can update the template with a reliable candidate at the right time while rejecting unreliable candidates. BackTrack is a generic template update scheme and is applicable to any template-based trackers. Extensive experiments on various tracking benchmarks verify the effectiveness of BackTrack over existing template update algorithms, as it achieves SOTA performance on various tracking benchmarks.Comment: 14 pages, 7 figure

Integrated Analysis of Permeability Reduction Caused by Polymer Retention for Better Understanding Polymer Transport

Polymer retention is one of the most important factors to govern polymer propagation through porous media, determining whether successful or not. The focus of previous studies has been limited to polymer concentration loss caused by the retention; not only change in polymer concentration, but also reduction in reservoir permeability is the main issue for theoretical transport study. Due to the lack of accuracy of Langmuir isotherm describing the polymer retention mechanisms, this study proposes a new type of matching interpretation method to correlate the permeability reduction factors from experiments to permeability. In order to solve the problem of poorly matching results between estimation and observation, use of nonadsorptive constant conditionally selected in matching process was made. Based on the threshold permeability reduction factors, approximate critical permeability can be calculated to which nonadsorptive constant would be applied. Results showed significant improvements in the estimation of permeability reduction for both low and high permeability cores. In addition, effects of permeability reduction on polymer transport in field scale were analyzed using the proposed matching model. Thus, not only does this interpretation method help to evaluate prediction for accurate flow behavior, but also unwanted risk can be evaluated

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs

Effects of abnormal cell-to-cell interference on p-type floating gate and control gate NAND flash memory

Abnormal cell-to-cell interference occurring in NAND flash memory has been investigated. In the case of extremely downscaled NAND flash memory, cell-to-cell interference increases abnormally. The abnormal cell-to-cell interference has been observed in a p-type floating gate (FG)/control gate (CG) cells for the first time. It has been found that the depletion region variation leads to the abnormal cell-to-cell interference. The depletion region variation of FG and CG is determined by state of neighbor cells. The depletion region variation affects CG-to-FG coupling capacitance and threshold voltage variation (Delta V-T). Finally, it is observed that there is a symmetrical relationship between n- and p-type FG/CG NAND flash memory in terms of cell-to-cell interference. (C) 2014 The Japan Society of Applied PhysicsN

Influence of Intercell Trapped Charge on Vertical NAND Flash Memory

The influence of intercell trapped charge (ITC)-the charge trapped at the inter-cell nitride regions by fringe electric fields during programand erase operations-on vertical NAND (VNAND) flash memory is investigated. In addition to conventional degradation mechanisms such as tunnel oxide damage, ITC deteriorates the transconductance and read current of VNAND flash memory cells. The influence of ITC-induced degradationon VNAND flashmemory is discussed, using both simulation and experimental results. A solution for ITC suppression is also proposed: the use of low-k intercell regions.N