VCI : a VHDL-C interface generation tool for cosimulation

International audienceThis paper deals with distributed cosimulation for heterogeneous systems prototyping. We presents a cosimulation environment who allows to handle all kinds of distributed architectures, any number of hardware or software modules, cosimulation at different abstraction levels, several cosimulation scenarios and smooth transition to the cosynthesis process. This flexibility is obtained thanks to an automatic cosimulation interface generation tool able to create the link between simulation environments. The advantages of our cosimulation methodology and more precisely the automatic cosimulation interface generation tool will be described by an example

Multilanguage Specification for System Design and Codesign

Communication TIME Computation Algorithms Specific Libraries FSMs, Exceptions Control Analytical Power (Formal Analysis) Cost of Use (standard, learning curve, hosts) Expressive power 19 SPW and COSSAP are two DSP oriented environments provided by EDA vendors. The fact that they are based on proprietary language make their cost of use quite high because of lack of standardization and generic tools supporting these languages. These environments also make extensive use of libraries which make formal verification difficult to apply

Open PROMOL: An Experimental Language for Target Program Modification

We present a short description of the capabilities of the experimental scripting language Open PROMOL. It has been developed aiming: 1) to deliver flexible means for representing wide range modifications of a target program, and 2) to support white-box reuse for well-understood domains, such as hardware design. We describe the syntax and semantics of the basic constructs of the language. We demonstrate the applicability of the language to perform modifications by widening, narrowing and isolating functionality in VHDL