Design of a WSN Platform for Long-Term Environmental Monitoring for IoT Applications

The Internet of Things (IoT) provides a virtual view, via the Internet Protocol, to a huge variety of real life objects, ranging from a car, to a teacup, to a building, to trees in a forest. Its appeal is the ubiquitous generalized access to the status and location of any "thing" we may be interested in. Wireless sensor networks (WSN) are well suited for long-term environmental data acquisition for IoT representation. This paper presents the functional design and implementation of a complete WSN platform that can be used for a range of long-term environmental monitoring IoT applications. The application requirements for low cost, high number of sensors, fast deployment, long lifetime, low maintenance, and high quality of service are considered in the specification and design of the platform and of all its components. Low-effort platform reuse is also considered starting from the specifications and at all design levels for a wide array of related monitoring application

Dynamic Trace-Based Data Dependency Analysis for Parallelization of C Programs

Writing parallel code is traditionally considered a difficult task, even when it is tackled from the beginning of a project. In this paper, we demonstrate an innovative toolset that faces this challenge directly. It provides the software developers with profile data and directs them to possible top-level, pipeline-style parallelization opportunities for an arbitrary sequential C program. This approach is complementary to the methods based on static code analysis and automatic code rewriting and does not impose restrictions on the structure of the sequential code or the parallelization style, even though it is mostly aimed at coarse-grained task-level parallelization. The proposed toolset has been utilized to define parallel code organizations for a number of real-world representative applications and is based on and is provided as free source

Algorithm validation and hardware design interactive approach

In this paper we will describe a modality to speed up the design of the VLSI digital (mainly DSP) circuits and to reduce the design errors by increasing the interaction between the ad-hoc software program developed to validate the algorithm and the VHDL description and simulation. A real case of a digital power analyzer will be used for exemplificatio

A high precision power supply meter

This paper describes an efficient implementation of a power supply meter. The implementation is based on the Fourier Series decomposition algorithm, using CORDIC algorithm for complex mathematical computations. It is able to calculate RMS and peak values, phase shift, power factor, and complex, active, and reactive power for two periodic waveforms up to the 25th harmonic. Several implementation alternatives are compared pointing out the advantages and the disadvantages of each one. Then the circuit structure at block level is described with emphasis on the advantages resulted from the use of CORDIC algorithm, followed by some considerations over precision issues

SystemC Model Generation for Realistic Simulation of Networked Embedded Systems

Verification and design-space exploration of today's embedded systems require the simulation of heterogeneous aspects of the system, i.e., software, hardware, communications. This work shows the use of SystemC to simulate a model-driven specification of the behavior of a networked embedded system together with a complete network scenario consisting of the radio channel, the IEEE 802.15.4 protocol for wireless personal area networks and concurrent traffic sharing the medium. The paper describes the main issues addressed to generate SystemC modules from Matlab/Stateflow descriptions and to integrate them in a complete network scenario. Simulation results on a healthcare wireless sensor network show the validity of the approach

Fast switched current analog memory

In this paper is presented the structure of a fast Switched Current (SI) analog memory and its integration with a high energy nuclear physics experiment equipment. A special emphasis is focused on the structure of the elementary memory cell, the SI flash A/D converter, and the sampling commands generation. There can be found also a short comparation of the SI and SC techniques for analog memories

A BiCMOS current carrier transceiver on low voltage power lines

This paper presents a BiCMOS technology project of a Current Carrier Transceiver (CCT) for data and digital broadcasting on Low Voltage (LV) power lines (230-240~Vac). The CCT is the central piece in using the LV power lines network as communication channel for various "intelligent" sensors, actuators, monitors, and remote control for domotic or industrial purpose

A BiCMOS current carrier transceiver on low voltage power lines

This paper presents a BiCMOS technology project of a Current Carrier Transceiver (CCT) for data and digital broadcasting on Low Voltage (LV) power lines (230-240~Vac). The CCT is the central piece in using the LV power lines network as communication channel for various "intelligent" sensors, actuators, monitors, and remote control for domotic or industrial purpose

Acceleration by Inline Cache for Memory-Intensive Algorithms on FPGA via High-Level Synthesis

Using FPGA-based acceleration of high-performance computing (HPC) applications to reduce energy and power consumption is becoming an interesting option, thanks to the availability of high-level synthesis (HLS) tools that enable fast design cycles. However, obtaining good performance for memory-intensive algorithms, which often exchange large data arrays with external DRAM, still requires time-consuming optimization and good knowledge of hardware design. This article proposes a new design methodology, based on dedicated application- and data array-specific caches. These caches provide most of the benefits that can be achieved by coding optimized DMA-like transfer strategies by hand into the HPC application code, but require only limited manual tuning (basically the selection of architecture and size), are neutral to target HLS tool and technology (FPGA or ASIC), and do not require changes to application code. We show experimental results obtained on five common memory-intensive algorithms from very diverse domains, namely machine learning, data sorting, and computer vision. We test the cost and performance of our caches against both out-of-the-box code originally optimized for a GPU, and manually optimized implementations specifically targeted for FPGAs via HLS. The implementation using our caches achieved an 8X speedup and 2X energy reduction on average with respect to out-of-the-box models using only simple directive-based optimizations (e.g., pipelining). They also achieved comparable performance with much less design effort when compared with the versions that were manually optimized to achieve efficient memory transfers specifically for an FPGA