Strained Silicon on Silicon by Wafer Bonding and Layer Transfer from Relaxed SiGe Buffer

We report the creation of strained silicon on silicon (SSOS) substrate technology. The method uses a relaxed SiGe buffer as a template for inducing tensile strain in a Si layer, which is then bonded to another Si handle wafer. The original Si wafer and the relaxed SiGe buffer are subsequently removed, thereby transferring a strained-Si layer directly to Si substrate without intermediate SiGe or oxide layers. Complete removal of Ge from the structure was confirmed by cross-sectional transmission electron microscopy as well as secondary ion mass spectrometry. A plan-view transmission electron microscopy study of the strained-Si/Si interface reveals that the lattice-mismatch between the layers is accommodated by an orthogonal array of edge dislocations. This misfit dislocation array, which forms upon bonding, is geometrically necessary and has an average spacing of approximately 40nm, in excellent agreement with established dislocation theory. To our knowledge, this is the first study of a chemically homogeneous, yet lattice-mismatched, interface.Singapore-MIT Alliance (SMA

Electron effective mobility in strained Si/Si1-xGex MOS devices using Monte Carlo simulation

Based on Monte Carlo simulation, we report the study of the inversion layer mobility in n-channel strained Si/ Si1-xGex MOS structures. The influence of the strain in the Si layer and of the doping level is studied. Universal mobility curves mueff as a function of the effective vertical field Eeff are obtained for various state of strain, as well as a fall-off of the mobility in weak inversion regime, which reproduces correctly the experimental trends. We also observe a mobility enhancement up to 120 % for strained Si/ Si0.70Ge0.30, in accordance with best experimental data. The effect of the strained Si channel thickness is also investigated: when decreasing the thickness, a mobility degradation is observed under low effective field only. The role of the different scattering mechanisms involved in the strained Si/ Si1-xGex MOS structures is explained. In addition, comparison with experimental results is discussed in terms of SiO2/ Si interface roughness, as well as surface roughness of the SiGe substrate on which strained Si is grown.Comment: 25 pages, 8 figures, 1 table, revised version, discussions and references adde

Selective SiGe nanostructures

Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2001.Includes bibliographical references (p. 206-215).Selective epitaxial growth (SEG) of SiGe on patterned SiO2/Si substrates by ultra-high vacuum chemical vapor deposition (UHVCVD) shows promise for the fabrication of novel SiGe microelectronic structures. This work explores selective growth conditions in the SiH2Cl2/SiH4/GeH4/H2 system between 650-850⁰C, without the addition of C12 or HC1, on substrates patterned by both conventional and interferometric lithography. We have achieved several important milestones for the fabrication of vertical MOSFETs by selective growth in 100 nm SiO2 features patterned by interferometric lithography. We have observed excellent selectivity to SiO2 masks with SiH2C12 at 750⁰C, perfect epitaxial Si filling of SiO2 features, the facet morphology during growth, and the effects of n-type doping on selective growth. We have also fabricated extremely sharp p-n diode doping profiles. With the above accomplishments we have demonstrated the feasibility of vertical MOSFET fabrication through selective epitaxial growth. To realize the advantages of advanced MOSFET designs on silicon-on-insulator (SOI) substrates, we have developed a facet-free raised source/drain process utilizing moderate n-type doping of Si selective growth and -oriented vertical SiO2 sidewalls. However, to improve SiO2 spacer dimension fidelity and eliminate Si substrate overetching, a novel SiO2/Si3N4 spacer process was developed. The keys to the SiO2/Si3N4 spacer process are removal of the Si3N4 layer prior to growth and increased Si ELO growth by moderate in situ n-type doping. This process has wide ranging application to both SOI and bulk Si technologies for fabrication of low-resistance contacts in advanced devices.(cont.) By a combination of interferometric lithography Si/SiO2 substrate patterning and Ge selective epitaxial growth, we have demonstrated threading dislocation blocking at the oxide sidewall which shows promise for dislocation filtering and the fabrication of low defect density Ge on Si for III-V device integration. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth (ELO) fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in any lattice-mismatched systems where dislocations are not parallel to growth directions. Investigation of Ge selective growth in micron-sized SiO2 features by plan-view TEM shows that substrate patterning on the order of microns is insufficient to filter dislocations in a large mismatch system ([epsilon] > 2%). Ge p-i-n photodetectors were selectively grown in micron-sized SiO2/Si features to correlate materials properties with electrical characteristics. For chemical protection and compatibility with Si microelectronics, Ge photodetector regions were capped with a thin n+ Si layer. Photodetectors fabricated on unpatterned substrates demonstrated leakage currents comparable to published results on Ge on Si photodetectors while leakage currents were noticeably degraded in devices grown on patterned substrates.by Thomas Andrew Langdo.Ph.D

Site controlled InAs/GaAs nanostructures on Si nano-tips

A novel strategy towards the scalable realization of site controlled III-V quantum dots on Si substrates is presented. The nano-heteroepitaxy of InAs/GaAs nanostructures on Si(001) nano-tips was evaluated by structural and optical characterization

Investigation of electrical properties of furnace grown gate oxide on strained-Si

10.1016/j.tsf.2004.05.028Thin Solid Films462-463SPEC. ISS.85-89THSF