Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-all-around stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer

Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI Devices

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Compact model of short-channel effects for FDSOI devices including the influence of back-bias and fringing fields for Si and III–V technology

International audienceIn this work, a compact model for short-channel effects is proposed for fully depleted silicon-on-insulator (FDSOI) MOSFETs, which takes into account the impact of body-bias and fringing fields, developed to be suitable for both thin and thick buried oxide (BOX) devices. The model is derived using the Voltage-Doping Transform, confirmed with TCAD simulations and experimental data from the literature. The impact of the BOX thickness on the subthreshold swing and the contribution of the leakiest path position to the DIBL are finally discussed

Doping profile extraction in thin SOI films: Application to A2RAM

session 1: Fabrication and Process characterizationInternational audienceWe propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the A2RAM performances. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data

Z 2 -FET DC hysteresis: Deep understanding and preliminary model

session 12: Future Devices (12.2)International audienceZ 2 -FET, a partially gated diode, was explored for ESD application due to its sharp switching behavior [1,2]. 1T-DRAM application of Z 2 -FET has recently been evidenced [3,4] leading to an even stronger interest for this device. However, a deep explanation of physical phenomena involved in Z 2 -FET operation has not been proposed yet. In this paper, we pro-vide a detailed description of the Z 2 -FET DC behavior based on TCAD simulations and propose corresponding analytical modeling

A2RAM Compact Modeling: From DC to 1T-DRAM Memory Operation

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Impact of quantum effects on the short channel effects of III-V nMOSFETs in weak and strong inversion regimes

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Z²-FET DC hysteresis: deep understanding and preliminary model

International audienceZ²-FET, a partially gated diode, was explored for ESD application due to its sharp switching behavior [1,2]. 1T-DRAM application of Z²-FET has recently been evidenced [3,4] leading to an even stronger interest for this device. However, a deep explanation of physical phenomena involved in Z²-FET operation has not been proposed yet. In this paper, we provide a detailed description of the Z²-FET DC behavior based on TCAD simulations and propose corresponding analytical modeling

Origins of the short channel effects increase in III-V nMOSFET technologies

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