Logic Errors in CMOS Circuits due to Simultaneous Switching Noise

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Analyzing the Logic Behavior of Digital CMOS Circuits in Presence of Simultaneous Switching Noise

International audienceThis paper analyzes the logic errors in digital circuits due to the presence of Simultaneous Switching Noise (SSN). It is demonstrated that 2 conditions must be fulfilled in order to guarantee the correct logic behaviour of a digital circuits. The first condition called ‘Minimum Switch Condition' is proved to be fulfilled whatever the amount of SSN in the power and ground lines. The second condition called ‘Signal Coherence Condition' is proved to be fulfilled within power coherent logic blocks. However the interface between non-coherent logic blocks may originate logic dysfunctio

Analyse de l'impact du bruit de commutation sur les blocs digitaux des circuits intégrés CMOS

MONTPELLIER-BU Sciences (341722106) / SudocSudocFranceF

Impact of Simultaneous Switching Noise on the Static Behavior of Digital CMOS Circuits

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On the Detection of SSN-Induced Logic Errors Through On-Chip Monitoring

International audienceSimultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the variations of power/ground lines at the interface between noncoherent logic blocks in order to warn that a logic error is likely to occur. This information can then be used for any scheme that takes corrective actions

On-Chip Monitor for the Detection of Logic Errors due to Simultaneous Switching Noise

International audienc