Data Communication Management in System Specification

In this paper, a powerful communication scheme is introduced to efficiently meet different communication requirements for behavioural synthesis from VHDL. The algorithmic description of the system behaviour is specified through a set of cooperating VHDL processes. Communication between processes is provided by the definition of a message--passing communication scheme, to efficiently manage both synchronised and unsynchronised data exchange. A way to effectively map message passing to shared memory for system synthesis is also presented. The proposed data communication scheme has been successfully tested with the VHDL model of the congestion control of an ATM node

A Hierarchical Control-Flow Model for System Synthesis

A new hierarchical model is described for the specification and management of control-flow information for system synthesis. This makes it possible to directly characterize and manage complex multithreaded control-flow structures, and to define in a powerful and compact way the execution semantics of the synthesis representation model

A Data-Flow Graph Representation for HDL Specification

A new data-flow graph representation is presented, which can be used in system level synthesis for the specification and management of a generic basic block node behavior. It is possible to flexibly specify and manage any composite data structure through the definition of a powerful representation scheme for arrays and records