The validation of the Hungarian version of the ID-migraine questionnaire

Despite its high prevalence, migraine remains underdiagnosed and undertreated. ID-Migraine is a short, self-administrated questionnaire, originally developed in English by Lipton et al. and later validated in several languages. Our goal was to validate the Hungarian version of the ID-Migraine Questionnaire.Patients visiting two headache specialty services were enrolled. Diagnoses were made by headache specialists according to the ICHD-3beta diagnostic criteria. There were 309 clinically diagnosed migraineurs among the 380 patients. Among the 309 migraineurs, 190 patients had only migraine, and 119 patients had other headache beside migraine, namely: 111 patients had tension type headache, 3 patients had cluster headache, 4 patients had medication overuse headache and one patient had headache associated with sexual activity also. Among the 380 patients, 257 had only a single type headache whereas 123 patients had multiple types of headache. Test-retest reliability of the ID-Migraine Questionnaire was studied in 40 patients.The validity features of the Hungarian version of the ID-Migraine questionnaire were the following: sensitivity 0.95 (95% CI, 0.92-0.97), specificity 0.42 (95% CI, 0.31-0.55), positive predictive value 0.88 (95% CI, 0.84-0.91), negative predictive value 0.65 (95% CI, 0.5-0.78), missclassification error 0.15 (95% CI, 0.12-0.19). The kappa coefficient of the questionnaire was 0.77.The Hungarian version of the ID-Migraine Questionnaire had adequate sensitivity, positive predictive value and misclassification error, but a low specificity and somewhat low negative predictive value

FPGA-based Low-cost Automatic Test Equipment for Digital Integrated Circuits

Digital circuits complexity and density are increasing while, at the same time, more quality and reliability are required. These trends, together with high test costs, make the validation of VLSI circuits more and more difficult. Beside high-end ATE machines, strictly necessary in ASIC production phase, low-cost ATE test systems take place into market to implement a valid support in ASIC development phase. In this paper a case study of low-cost, reconfigurable, versatile and easy-to-use FPGA-based test environment is presented. It allows patterns to be extracted from HDL-simulation and stimuli to be generated to ASIC prototypes, especially when a high-end test machine setup isn't foreseen or isn't available yet. This is the ideal solution for engineers to develop test programs and perform device tests and yield analysis on their desktop and then transfer the test program directly to production. The result is low-cost automatic test equipment, able to execute a preliminary digital test, using just a Laptop and an FPGA-equipped board

FPGA-Based Advanced Digital Signal Inspector for Internal Signals of Pin-limited Systems-on-Package

The paper presents an Advanced Digital Signal Inspector (ADSI) used for acquisition and analysis of the internal digital of a System on Package (SoP) with a limited number of pins. The system is made of a commercial FPGA-board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed platform can be used to extract and monitor simultaneously up to 4 digital signals, and an ADC is used to monitor one additional analog signal. The ADSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning. The ADC was connected to an external accelerometer to evaluate the module behaviour when applying mechanical shocks

Digital Signal Inspector for internal signals of pin-limited systems on package

The paper presents a Digital Signal Inspector (DSI) able to monitor the internal digital signals of a System on Package (SoP) with a limited number of pins. The DSI is made of a commercial FPGA-board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed DSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning

Pin-limited frequency downscaler AHB bridge for ASIC to FPGA communication

Output connections to out-of-chip devices in modern mixed-signal ICs represent a significant design problem due to the limited number of available pins (in not Ball Grid Array package) and to the common need of a frequency reduction, especially into systems that require an external System on Programmable Chip (SoPC). In this paper, an ASIC solution based on bisynchronous FIFO structures for frequency conversion is presented. The proposed bridge involves a custom protocol for the conversion of the transmitted data in low frequency and low width bus. Moreover, it allows managing data transmission with two different priority levels. The module is AHB lite compliant with a number of pins equal to the width of the FIFOs (configurable during implementation phase) and two handshaking signals. Output clock frequency and internal FIFOs dimension are user-defined too

A Dynamic Clock Switch for Automotive System on Chip

One of the key-points in System on Chip (SoC) design is to have the proper clock oscillator. Currently the most used are RC and quartz oscillators. They feature different characteristics in terms of performance, power consumption and cost, both oscillators have their own advantages and drawbacks. Sometimes SoC design would benefit to have both solutions in order to best cope with all requirements. This calls for an integrated architecture to dynamically switch between the two clock signals. In this paper we present a new parametric architecture able to handle a generic number of clock signals allowing the dynamic switch from one clock to the other. The detailed structure is here shown and an accurate timing analysis is also presented to prove its robustness and the absence of glitch on output clock signal. FPGA and 0.35 μm CMOS implementations are presented for an automotive SoC design

Great occipital nerve blockade for cluster headache in the emergency department: case report

A 44-year-old man with a past medical history of episodic cluster headache presented in our ED with complaints of multiple daily cluster headache attacks, with cervico-occipital spreading of pain from May to September 2004. The neurological examination showed no abnormalities as well as brain and spine MRI. Great Occipital Nerve (GON) blockade, with Lidocaine 2% (5 ml) and betamethasone (2 mg), were performed in the right occipital region (ipsilaterally to cluster headache), during attack. GON blockade was effective immediately for the attack and the cluster period resolved after the injection. We suppose that the action of GON blockade may involve the trigemino-cervical complex and we moreover strongly suggest to use GON blockade in emergency departments for cluster headache with cervico-occipital spreading as attack abortive therapy, especially in oxygen and sumatriptan resistant cluster headache attacks, in patients who complaints sumatriptan side-effects or have contraindications to use triptans

Efficient Acquisition and Analysis of Digital Signals in Pin-limited System-on-Package

The paper presents an Advanced Digital Signal Inspector (ADSI) used for acquisition and analysis of the internal digital of a System on Package (SoP) with a limited number of pins. The system is made of a commercial FPGA-board, connected to the module for data sampling and controlled by PC via USB; a suited graphical interface allows for configuration, multi trace real time data display and post processing. The proposed platform can be used to extract and monitor simultaneously up to 4 digital signals, and an ADC is used to monitor one further analog signal. The ADSI has been successfully applied for the characterization of an automotive SoP based on a MEM gyro sensor interfaced to an ASIC for proper signal conditioning. The ADC was connected to an external accelerometer to evaluate the SoP behaviour when applying mechanical shocks