Silicon nanowires with lateral uniaxial tensile stress profiles for high electron mobility gate-all-around MOSFETs

In this work we present for the first time correlation of lateral uniaxial tensile strain and I–V characteristics of GAA Si NW n-MOSFET, all measured on the same device. Micro-Raman spectroscopy is employed for direct strain measurement on devices to exploit the main sources of process-induced strain, found to be accumulation of mechanical potential energy in the Si NWs during local oxidation and releasing it in the form of local lateral uniaxial tensile stress in the Si NW by out-of-plane mechanical buckling as well as lateral in-plane elongation during stripping the hard mask and the grown oxide. A triangular GAA Si NW with 0.6 GPa peak of lateral uniaxial tensile stress, fabricated using this bulk top-down technology, exhibits promising improvements e.g. of the normalized drain current (ID/Weff) up to 38%, of the transconductance (gm/Weff) up to 50%, of the low field mobility by 53% with a peak of 64% in the peak stress region, compared to a reference device. The mobility extraction originally takes into account the measured strain profile in the channel

A quasi-analytical model for nanowire FETs with arbitrary polygonal cross section

In this work a quasi-analytical physical model has been developed for the prediction of the potential in SiNW devices with arbitrary polygonal cross section. The model is then extended to the transport direction; a method for the calculation of the natural channel length has been proposed and validated by means of 2D and 3D numerical device simulations. With the results based on the proposed model it is possible to compare nanowires with cross sections of different shape and predict the minimum technological gate length able to assure immunity to the SCEs

Corner Effect and Local Volume Inversion in SiNW FETs

In this paper, a quantitative study of the corner effect and of the local volume inversion on gate-all-around MOSFETs based on numerical simulations has been carried out; different angles and doping levels are compared, in order to understand the impact of the corner regions on the total current. A method for the extraction of the threshold voltage and of the subthreshold slope of the corner region has been proposed, and the resulting values have been analyzed in order to understand their effects on the device characteristics

Tunneling path impact on semi-classical numerical simulations of TFET devices

In this work a non-local band-to-band tunnelling model has been implemented into a full-band Monte Carlo simulator. Two different approaches for the choice of the tunnelling path have been implemented and their impact on the transfer characteristics of different Tunnel FET structures is investigated. In both the SOI and the DG TFET architectures we have simulated, up to 1 order of magnitude of underestimation in the current and up to 15% of difference in the value of the Subthreshold Slope can be found according to the choice of the tunnelling path

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism [1]. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications [2]. Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA) [3,4]. Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. © 2011 IEEE

On the Surface-Roughness Scattering in Biaxially Strained n- and p-MOS Transistors

Electron- and hole-mobility enhancements in biaxially strained metal\u2013oxide\u2013semiconductor transistors are still a matter for active investigation, and this brief presents a critical examination of a recently proposed interpretation of the experimental data, according to which the strain significantly modifies not only the root-mean-square value but also the correlation length of the surface-roughness spectrum.We present a systematic comparison between comprehensive numerical simulations and experiments, which supports such an interpretation

The p-ring Trench Schottky IGBT: A solution towards latch-up immunity and an enhanced safe-operating area

A novel Trench IGBT design, namely the p-ring Trench Schottky IGBT, with improved latch-up immunity and an enhanced safe-operating area is proposed. This design improves the performance of the FS+ IGBT by facilitating the collection of holes through a p-doped (p-ring) buried region connected through a Schottky contact to the source/cathode contact. This unique structure approach allows the improvement in the device reliability and it is shown under numerical studies to be highly effective in expanding the safe operating area (SOA), suppress dynamic avalanche, improve the latch up robustness and have the potential to improve the device switching operation

Tunnel-FET architecture with improved performance due to enhanced gate modulation of the tunneling barrier

5The Tunnel-FET (TFET) device is a gated reverse biased p-i-n junction whose working principle is based on the quantum mechanical Band-to-Band Tunneling (B2BT) mechanism. The OFF-ON transition can be much more abrupt than for conventional MOSFETs, thus allowing a reduction of the supply voltage and power consumption in logic applications . Several TFETs with point Subthreshold Swing (SS) lower than 60mV/dec have been experimentally demonstrated with different architectures as conventional single gate Silicon-on-Insulator (SOI), Double Gate (DG) and Gate-All-Around (GAA). Unfortunately in all cases a relatively large average SS and a poor on-current have been observed. In conclusion with this work we have shown that although commonly fabricated TFETs feature source/channel interfaces normal to the transport direction, in a well-designed TFET the tunneling junction should have the same orientation of the component of the electric field modulated by the gate: only in this case the gate can effectively modulate the tunneling barrier, resulting in a steeper average SS and higher ION.reservedmixedDe Michielis L; Lattanzio L; Palestri P; Selmi L; Ionescu A. M.DE MICHIELIS, Luca; Lattanzio, L; Palestri, Pierpaolo; Selmi, Luca; Ionescu, A. M