Nanoelectromechanical (NEM) Devices for Logic and Memory Applications

© 2022, Institute of Electronics Engineers of Korea. All rights reserved.—Recent research on NEM devices for logic and memory applications has been reviewed from the perspective of monolithic 3D (M3D) heterogeneous integration. In addition, the backgrounds of M3D CMOS-NEM reconfigurable logic (RL) circuits are described in detail. Moreover, 65-nm process based M3D CMOS-NEM RL circuits were proposed. It is predicted that proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.N

Slingshot Pull-In Operation for Low-Voltage Nanoelectromechanical Memory Switches

A novel "slingshot" pull-in operation is proposed to lower the operation voltage (V-DD) of nanoelectromechanical (NEM) memory switches for the implementation of monolithic 3-D (M3D) CMOS-NEM hybrid reconfigurable logic (RL) circuits. According to the theoretical calculation and experimental data, the proposed "slingshot" pull-in operation lowers V-DD of the NEM memory switches by similar to 0.84 times. It contributes to the overall V-DD reduction and chip density boost of M3D CMOS-NEM RL circuits.N

Multi-Layer Nanoelectromechanical (NEM) Memory Switches for Multi-Path Routing

Monolithic three-dimensional (M3D) multilayer nanoelectromechanical (NEM) memory switches are experimentally demonstrated for reconfigurable multi-path routing. The multi-layer NEM memory switch has moving mechanical beams in different metal layers which operate independently in a nonvolatile manner, including high impedance states. For example, double-layer NEM memory switches implement nine different memory states. It is predicted that our proposed n-layer NEM memory switches utilizing n metal layers will exhibit 3((n-1)) x higher routing flexibility and nx higher chip density than conventional single-layer NEM memory switches.N

Island-Style Monolithic Three-Dimensional CMOS-Nanoelectromechanical Logic Circuits

Island-style monolithic three-dimensional (M3D) CMOS- nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated showing the full operation of the island-style RL: single-tile and tile-to-tile operation. For the fabrication of M3D CMOS-NEM RL circuits, 65-nm CMOS baseline process was used, in which copper NEM memory switches are integrated over the CMOS logic circuits by using dual damascene process. It is predicted that our proposed M3D CMOS-NEM RL circuits will exhibit 4.6x higher chip density, 2.3x higher operation frequency and 9.3x lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.N

Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation

Monolithic three-dimensional (M3D) CMOS-nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated. This is the first experimental demonstration of 65-nm M3D CMOS-NEM RL circuits satisfying the 1.2-V supply voltage (VDD) requirement of the 65-nm technology node. The fabrication process is identical to the conventional 65-nm CMOS baseline process, in which copper NEM memory switches are formed by a dual damascene process.N

Influence of Channel Hole Remaining Ratio on Hemi-Cylindrical Vertical NAND Flash Memory

The influence of the channel hole remaining ratio (CHRR) on the hemi-cylindrical (HC) vertical NAND (VNAND) flash memory was investigated using both simulation and experimental data. Although HC VNAND flash memory is advantageous for increasing lateral memory density, it suffers from nonuniform carrier injection and low program/erase efficiency. In this study, the underlying physics of these disadvantages are discussed in terms of the proposed parameter, CHRR. Finally, based on the analysis, a recessed channel HC VNAND flash memory cell is proposed.N

Switching Voltage Analysis of Nanoelectromechanical Memory Switches for Monolithic 3-D CMOS-NEM Hybrid Reconfigurable Logic Circuits

The accurate calculation of switching voltage (V-s) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because V-s corresponds to the operating voltage (V-dd) of NEM memory switches. In this paper, based on the Euler-Bernoulli equation, the physics-based analytical model is proposed to determine V-s. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum V-s (V-s_(m)) and device dimensions.N

Active Region Formation of Nanoelectromechanical (NEM) Devices for Complementary-Metal-Oxide-Semiconductor-NEM Co-Integration

Considering the isotropic release process for nanoelectromechanical (NEM) devices, defining the specific sacrificial layer of the inter-metal-dielectric (IMD), i.e., the active region only for NEM devices, is one of the most important issue for complementary-metal-oxide-semiconductor-NEM (CMOS-NEM) co-integrated circuits. In this paper, novel fabrication method to define the active region of NEM devices is proposed by forming the trenched mesa-shape pattern in the IMD and depositing aluminum oxide (Al2O3) protecting layer. By applying the proposed process, the void space for mechanical operation of NEM devices can be formed user-controllably without the damage and collapse of CMOS part located below the NEM part. The feasibility of the proposed process is verified by fabricating and measuring the proof-of-concept prototype consists of the aluminum (Al) interconnects, silicon dioxide (SiO2) IMD and NEM memory switches.N