Doubling speed using strained Si/SiGe CMOS technology

The benefit of high performance strained Si CMOS in terms of technology generations is quantified. It is shown that a 0.3 μm gate length strained Si/Si0.75Ge0.25 CMOS technology has the same gate delay as conventional technology having an effective gate length of 0.14 μm, but without the cost of re-tooling. Transconductance enhancements over conventional CMOS in excess of 200% are demonstrated for surface channel n- and p-MOSFETs using a Si0.75Ge0.25 virtual substrate without CMP and a high thermal budget process. To our knowledge these represent the best results reported to date at these dimensions

Study of single- and dual-channel designs for high-performance strained-Si-SiGe n-MOSFETs

Results comparing strained-Si-SiGe n-channel MOSFET performance of single-and dual-surface channel devices fabricated using 15% Ge content SiGe virtual substrates are presented. Device fabrication used high thermal budget processes and virtual substrates were not polished. Mobility enhancement factors exceeding 1.6 are demonstrated for both single-and dual-channel device architectures compared with bulk-Si control devices. Single-channel devices exhibit improved gate oxide quality, and larger mobility enhancements, at higher vertical effective fields compared with the dual-channel strain-compensated devices. The compromised performance enhancements of the dual-channel devices are attributed to greater interface roughness and increased Ge diffusion resulting from the Si/sub 0.7/Ge/sub 0.3/ buried channel layer

High-Performance nMOSFETs Using a Novel Strained Si/SiGe CMOS Architecture

Performance enhancements of up to 170% in drain current, maximum transconductance, and field-effect mobility are presented for nMOSFETs fabricated with strained-Si channels compared with identically processed bulk Si MOSFETs. A novel layer structure comprising Si/Si0.7Ge0.3 on an Si0.85Ge0.15 virtual substrate (VS) offers improved performance advantages and a strain-compensated structure. A high thermal budget process produces devices having excellent on/off-state drain-current characteristics, transconductance, and subthreshold characteristics. The virtual substrate does not require chemical-mechanical polishing and the same performance enhancement is achieved with and without a titanium salicide process

Optimization of alloy composition for high-performance strained-Si-SiGeN-channel MOSFETs

On-state and off-state performance of strained- Si–SiGe n-channel MOSFETs have been investigated as a function of SiGe virtual substrate alloy composition. Performance gains in terms of on-state drain current and maximum transconductance of up to 220% are demonstrated for strained-Si–SiGe devices compared with Si controls. Device performance is found to peak using a virtual substrate composition of Si0.75Ge0.25. MOSFET fabrication used high thermal budget processing and good gate oxide quality has been maintained for virtual substrates having Ge compositions up to 30%. Off-state characteristics are found to be more sensitive to strain relaxation than on-state characteristics. <br/

Thermal oxidation of strained Si/SiGe: impact of surface morphology and effect on MOS devices

The performance of surface channel MOS devices depends on gate oxide interface quality. Carrier transport is enhanced in strained Si, thus its use for MOSFET channels can increase device performance. Thermal oxidation produces the highest quality SiO2. This paper compares thermal oxidation of strained Si with unstrained Si. Strained Si is achieved by epitaxial growth on relaxed SiGe. The impact of large-scale cross-hatching roughness inherent in relaxed SiGe alloys on strained Si oxidation is investigated. The nanoscale oxide interface roughness and oxidation rate of strained Si are found to correlate with the undulating cross-hatch period, increasing and decreasing, respectively, with the degree of surface vicinality. Further, analysis suggests strained Si oxidation kinetics arise primarily from local variations in the SiGe substrate orientation due to cross-hatching, rather than strain. Devices fabricated on relatively smooth SiGe material exhibit electrical performance enhancements exceeding 75% compared with devices fabricated on material with severe cross-hatching. Likely causes for the dependence of strained Si oxidation kinetics on surface morphology and the impact on MOS devices are discussed. The enhanced performance of strained Si/SiGe MOSFETs over Si control devices with equivalent oxide interface roughness is also presented. Strained Si devices exhibit mobility gains greater than 100% and significant increases in transconductance compared with control devices