Electrical properties of plasma-deposited silicon oxide clarified by chemical modeling

Our study is focused on Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide films at low temperatures (< 150 oC) using Inductively Coupled (IC) High-Density (HD) plasma source. We recently fabricated Thin Film Transistors (TFTs) with high-quality ICPECVD gate oxides, which exhibited a competitive performance. For better understanding of the influence of deposition parameters on both the deposition kinetics and oxide quality, we have modeled the Ar-SiH4-N2O plasma system with 173 chemical reactions. We simulated concentrations of 43 reactive species (such as e.g. SiHx radicals and SiHx + (x=0-3) ions, polysilanes, SiO, SiN, SiH3O, SiH2O, HSiO, etc., as well as atomic hydrogen, nitrogen and oxygen) in plasma. We further used our simulations to qualitatively explain (in terms of concentrations of the reactive species) the influence of SiH4/N2O gas-flow ratio and total gas pressure on film electrical properties and deposition rate

Atmospheric-pressure atomic layer deposition:recent applications and new emerging applications in high-porosity/3D materials

Atomic layer deposition (ALD) is a widely recognized technique for depositing ultrathin conformal films with excellent thickness control at Ångström or (sub)monolayer level. Atmospheric-pressure ALD is an upcoming ALD process with a potentially lower ownership cost of the reactor. In this review, we provide a comprehensive overview of the recent applications and development of ALD approaches emphasizing those based on operation at atmospheric pressure. Each application determines its own specific reactor design. Spatial ALD (s-ALD) has been recently introduced for the commercial production of large-area 2D displays, the surface passivation and encapsulation of solar cells and organic light-emitting diode (OLED) displays. Atmospheric temporal ALD (t-ALD) has opened up new emerging applications such as high-porosity particle coatings, functionalization of capillary columns for gas chromatography, and membrane modification in water treatment and gas purification. The challenges and opportunities for highly conformal coating on porous substrates by atmospheric ALD have been identified. We discuss in particular the pros and cons of both s-ALD and t-ALD in combination with their reactor designs in relation to the coating of 3D and high-porosity materials.</p

On The Growth Of Native Oxides On Hydrogen- Terminated Silicon Surfaces In Dark And Under Illumination With Light

After a cleaning procedure, a silicon surface can be terminated by Si-OH groups which results in a high chemical activity. As it is accepted, after removing the wet-chemically grown oxide layer using an HF solution, the surface becomes terminated with Si-H groups. This results in a chemically stable surface (e.g., retarded formation of native oxide). The stability over a period of several hours is reported [1]. Low-temperature processes, including deposition of extremely thin layers, are playing an increasingly important role in modern IC manufacturing. Surface conditions prior to the film deposition can significantly influence interface properties and deposition kinetics. A low temperature results in a limited possibility to activate the surface prior to the deposition. For a stable hydrogenterminated silicon substrate, the surface activation means reducing its chemical stability caused by the Si-H groups, i.e., desorption of hydrogen from the Si-H bonds. In this work, we investigated the thickness evolution of native oxides formed on a silicon surface terminated by Si-H groups. Apart from measuring the kinetics of such native oxidation, this should reflect the surface stability over a period of time. The native oxidation in dark was compared with similar oxidation stimulated by the illumination with a 20 W Halogene lamp, having a very low UV emission. To the best of our knowledge, the systematic investigation of the kinetics of the native oxidation of p and n-type silicon, especially concerning the influence of light on this process is very limited. The native oxidation at room temperature was compared with a wet oxidation at 250 o C in an ALD reactor. The oxide thickness was measured at different exposure times to air, varying from several minutes to several days. The oxide growth on both p-type and n-type silicon wafers was compared. We used (100)-oriented silicon wafers with a resistivity of 2-5 Ω⋅cm. All the wafers were subjected to the same cleaning procedure. Cleaning started with a 10-min immersion into fuming HNO 3 at room temperature, followed by a rinse in DI water for several minutes. Then, the wafers were immersed into boiling HNO 3 (60%) for 10 min, followed by a similar rinse in DI water. Further, the wafers suffered from a 30-s dip into a 1% HF solution, resulted in a hydrophobic surface. A 2-min rinse in DI water followed by a 60-s drying using a spinner (both performed in dark) finalized the cleaning process. The oxide thickness was measured using a modified Kratos XSAM800 XPS apparatus. We used the same model as described in [2] to fit the Si 2p3/2 peak to different oxidation states of silicon. The quantitative data on oxide thickness were calculated from the peak areas. In To describe the growth kinetics of native oxides on silicon in a satisfactory manner, we continued developing the oxidation model earlier published i

Langmuir-probe characterization of an inductively-coupled remote plasma system intended for CVD and ALD

We measured electron density and electron energy distribution function (EEDS) vertically through our reactor for a range of process conditions and for various gases. The EEDF of Ar plasma in the reactor could largely be described by the Maxwell-Boltzmann distribution function, but it also contained a fraction (~10-3) of electrons which were much faster (20-40 eV). At low pressures (6.8-11 µbar), the tail of fast electrons shifted to higher energies (Emax ~50 eV) as we measured more towards the chuck. This tail of fast electrons could be shifted to lower energies (Emax ~30 eV) when we increased pressure to 120 µbar or applied an external magnetic field of 9.5 µT. Addition of small amounts of N2 (1-10%) or N2O (5%) to Ar plasma lowered the total density of slow electrons (approx. by a factor two) but did not change the shape of the fast-electron tail of the EEDF. The ionization degree of Ar-plasma increased from 2.5 104 to 5 104 when an external magnetic field of 9.5 µT was applied

Negative Charge in Plasma Oxidized SiO2 Layers

Silicon dioxide (SiO2) gate dielectric layers (4-60 nm thick) were deposited (0.6 nm/min) on n-type Si by inductively-coupled plasmaenhanced chemical vapor deposition (ICPECVD) in strongly diluted silane plasmas at 150°C . In contrast to the well-accepted positive charge for thermally grown SiO2, the net oxide charge was negative and a function of the layer thickness. Our experiments suggested that the negative charge was created due to unavoidable oxidation of the silicon surface by plasma species, and the CVD component adding a positive space charge to the deposited oxide. The net charge was negative under process conditions where plasma oxidation played a major role. Such conditions included low deposition rates and relatively thin grown layers. Additional measurements showed that the negative charge in SiO2 also persisted on p-type substrates. We suggest that plasma oxidation of the silicon surface results in SiO2 layers with a surplus of oxygen. This surplus of oxygen is able to accumulate a negative charge. This assumption is addressed in this paper by a review of earlier work on silicon oxidation, and by a first series of experiments wherein oxygen is implanted into thermal SiO2. It is shown that the implantation can result in a negative charge to the bulk oxide layer. The effect of the negative charge on the flatband voltage can be described by the implantation profile

Low-temperature fabricated TFTs on polysilicon stripes

This paper presents a novel approach to make highperformance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/V • s (NMOS) and 128 cm2/V • s (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration