4 research outputs found
Enabling hardware randomization across the cache hierarchy in Linux-Class processors
The most promising secure-cache design approaches use cache-set randomization to index cache contents thus thwarting cache side-channel attacks. Unfortunately, existing randomization proposals cannot be sucessfully applied to processorsâ cache hierarchies due to the overhead added when dealing with coherency and virtual memory. In this paper, we solve existing limitations of hardware randomization approaches and propose a cost-effective randomization implementation to the whole cache hierarchy of a Linux-capable RISC-V processor.This work has been supported by the European HiPEAC Network of Excellence, by the Spanish Ministry of Economy and Competitiveness (contract TIN2015-65316-P), and by Generalitat de Catalunya (contracts 2017-SGR-1414 and 2017- SGR-1328). The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total cost eligible. We also thank Red-RISCV for the efforts to promote activities around open hardware. This work has received funding from the EU Horizon2020 programme under grant agreement no. 871467 (SELENE). M. Doblas has been partially supported by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under Beques de Col·laboraciĂł dâestudiants en departaments universitaris per al curs 2019- 2020. V. Kostalabros has been partially supported by the Agency for Management of University and Research Grants (AGAUR) of the Government of Catalonia under Ajuts per a la contractaciĂł de personal investigador novell fellowship number 2019FI_ B01274. M. Moreto has been partially supported by the Spanish Ministry of Economy, Industry and Competitiveness under RamĂłn y Cajal fellowship number RYC- 2016-21104.Peer ReviewedPostprint (published version
DVINO: A RISC-V vector processor implemented in 65nm technology
This paper describes the design, verification, implementation and fabrication of the Drac Vector IN-Order (DVINO) processor, a RISC-V vector processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The DVINO processor includes an internally developed two-lane vector processor unit as well as a Phase Locked Loop (PLL) and an Analog-to-Digital Converter (ADC). The paper summarizes the design from architectural as well as logic synthesis and physical design in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedArticle signat per 43 autors/es: Guillem Caboâ, Gerard CandĂłnâ, Xavier Carrilâ, Max Doblasâ, Marc DomĂnguezâ, Alberto GonzĂĄlezâ, Cesar HernĂĄndezâ , VĂctor JimĂ©nezâ, Vatistas Kostalamprosâ, RubĂ©n Langaritaâ, Neiel Leyvaâ , Guillem LĂłpez-ParadĂsâ, Jonnatan Mendozaâ, Francesco Minerviniâ, Julian PavĂłnâ, Cristobal RamĂrezâ, NarcĂs Rodasâ, Enrico Reggianiâ, Mario RodrĂguezâ, Carlos Rojasâ, Abraham Ruizâ, VĂctor Soriaâ, Alejandro SuanesâĄ, IvĂĄn Vargasâ, Roger Figuerasâ, Pau Fontovaâ, Joan Marimonâ, VĂctor Montabesâ, AdriĂĄn Cristalâ, Carles HernĂĄndezâ, Ricardo MartĂnezâĄ, Miquel MoretĂłâ§, Francesc Mollâ§, Oscar Palomarâ§, Marco A. RamĂrezâ , Antonio Rubio§, Jordi SacristĂĄnâĄ, Francesc Serra-GraellsâĄ, Nehir Sonmezâ, LluĂs TerĂ©sâĄ, Osman Unsalâ, Mateo Valeroâ§, LuĂs Villaâ // âBarcelona Supercomputing Center (BSC), Barcelona, Spain. Email: [email protected]; â Centro de InvestigaciĂłn en ComputaciĂłn, Instituto PolitĂ©cnico Nacional (CIC-IPN), Mexico City, Mexico; ⥠Institut de Microelectronica de Barcelona, IMB-CNM (CSIC), Spain. Email: [email protected]; §Universitat Politecnica de Catalunya (UPC), Barcelona, Spain. Email: [email protected] (author's final draft
An academic RISC-V silicon implementation based on open-source components
©2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.The design presented in this paper, called preDRAC, is a RISC-V general purpose processor capable of booting Linux jointly developed by BSC, CIC-IPN, IMB-CNM (CSIC), and UPC. The preDRAC processor is the first RISC-V processor designed and fabricated by a Spanish or Mexican academic institution, and will be the basis of future RISC-V designs jointly developed by these institutions. This paper summarizes the design tasks, for FPGA first and for SoC later, from high architectural level descriptions down to RTL and then going through logic synthesis and physical design to get the layout ready for its final tapeout in CMOS 65nm technology.The DRAC project is co-financed by the European Union Regional Development Fund within the framework of the ERDF Operational Program of Catalonia 2014-2020 with a grant of 50% of total eligible cost. The authors are part of RedRISCV which promotes activities around open hardware. The Lagarto Project is supported by the Research and Graduate Secretary (SIP) of the Instituto Politecnico Nacional (IPN) Ž from Mexico, and by the CONACyT scholarship for Center for Research in Computing (CIC-IPN).Peer ReviewedPostprint (author's final draft