EM emission of ICs implementated in FPGA : influence of floor plan and electric function

In the paper some investigations are presented aiming to check the influence of IC floor plan and the circuit function on its electromagnetic emissions. As the test vehicle Xilinx FPGA XCV800 type was used, in which two types of multiplicators were implemented. To compare the effects, high frequency currents in supply and ground pins of the circuits as well as near field disturbances were measured over the circuits

Countdown μ-calculus

We introduce the countdown μ-calculus, an extension of the modal μ-calculus with ordinal approximations of fixpoint operators. In addition to properties definable in the classical calculus, it can express (un)boundedness properties such as the existence of arbitrarily long sequences of specific actions. The standard correspondence with parity games and automata extends to suitably defined countdown games and automata. However, unlike in the classical setting, the scalar fragment is provably weaker than the full vectorial calculus and corresponds to automata satisfying a simple syntactic condition. We establish some facts, in particular decidability of the model checking problem and strictness of the hierarchy induced by the maximal allowed nesting of our new operators

Electromagnetic emission of digital circuits implemented in Xilinx FPGAs XC 4025E and XCV 800

The results of testing electromagnetic emissions generated by circuits implemented in Xilinx FPGAs XC 4025E and XCV 800 types are presented. Both radiated and conducted emissions of the circuits were measured as a function of cIock frequency. Possible practical recommendations are discussed

Niskonapięciowy szybki czteroćwiartkowy trans-konduktancyjny układ mnożący w technologii cmos

The paper presents an analog four-quadrant transconductance multiplier designed in CMOS technology, suitable for low voltage and operating at high-speed. The transconductance multiplier with Gilbert-like architecture uses a cascade of a combination of two linear current dividers implemented by means of the differential pairs to produce a linear dependence between the tail current and the two output currents. To adopt the circuit for low voltage, simple current mirrors have been applied to couple the first- and the second stage of the current dividers cascade. High-speed operation is possible thanks to simple architecture of building blocks using RF CMOS transistors with sufficiently large biasing currents. A complete circuits schematic with input driving peripherials, as well as simulation results of entire multiplier have also been presented.W artykule zaprezentowano szybki niskonapięciowy czteroćwiartkowy układ mnożący zaprojektowany w technologii CMOS. Architektura układu oparta jest o strukturę typu Gilberta. W układzie zastosowano kaskadowe połączenie dwóch stopni transkonduktancyjnych zrealizowanych w oparciu o pary różnicowe. Aby układ mógł pracować w zakresie niskich napięć zasilających poszczególne stopnie zostały sprzęgnięte przy pomocy prostych luster prądowych. Duża szybkość działania została osiągnięta dzięki prostej architekturze układu oraz zastosowaniu tranzystorów RF pracujących przy odpowiednio dużych wartościach prądów. W pracy zaprezentowano również wejściowe niskonapięciowe bloki pomocnicze oraz wyniki symulacji kompletnego układu mnożącego

Hybrid Linearized Class-BD Double Sided (LBDD) Digital Pulse Width Modulator (DPWM) for Class-BD audio amplifiers

The paper presents an original architecture and implementation of 9-bit LBDD hybrid DPWM circuit for Class-BD digital audio amplifier. The input PCM signals are directly transformed into 24-bit LBDD DPWM signals and then are requanized to the 9-bit digital outputs using noise-shaping process to support high fidelity with practical values of time resolution, and finally are converted by the DTCs into the two physical trains of 1-bit PWM signals. The architecture of the proposed Class-BD hybrid DPWM circuit is composed of two Class-AD ones. The hybrid quantizer converts 6 MSB bits using counter method, based on the STM32F407xx microcontroller, while the remaining 3 LSB bits - using a method based on the Programmable Tapped Delay Line (PTDL). All necessary time waveforms are generated on the base of the internal microcontroller oscillator 168 MHz. The proposed 9-bit Class-DB DPWM circuit allows to attain SNR of 110 dB and THD about 0,2% within the audio baseband, at switching frequency of 328.1 kHz, clock frequency of 42 MHz and modulation index M = 0.95. Basic verification of algorithm and circuit operation as well as simulation and preliminary experimental results have been performed