Ultraviolet photoconductive devices with an n-GaN nanorodgraphene hybrid structure synthesized by metal-organic chemical vapor deposition

The superior photoconductive behavior of a simple, cost-effective n-GaN nanorod (NR)-graphene hybrid device structure is demonstrated for the first time. The proposed hybrid structure was synthesized on a Si (111) substrate using the high-quality graphene transfer method and the relatively low-temperature metal-organic chemical vapor deposition (MOCVD) process with a high V/III ratio to protect the graphene layer from thermal damage during the growth of n-GaN nanorods. Defect-free n-GaN NRs were grown on a highly ordered graphene monolayer on Si without forming any metal-catalyst or droplet seeds. The prominent existence of the undamaged monolayer graphene even after the growth of highly dense n-GaN NRs, as determined using Raman spectroscopy and high-resolution transmission electron microscopy (HR-TEM), facilitated the excellent transport of the generated charge carriers through the photoconductive channel. The highly matched n-GaN NR-graphene hybrid structure exhibited enhancement in the photocurrent along with increased sensitivity and photoresponsivity, which were attributed to the extremely low carrier trap density in the photoconductive channelclose00

Semiconductor device comprising a heterojunction

A semiconductor device with a heterojunction. The device comprises a substrate and at least one nanostructure. The substrate and nanostructure is of different materials. The substrate may e.g. be of a group IV semiconductor material, whereas the nanostructure may be of a group III-V semiconductor material. The nanostructure is supported by and in epitaxial relationship with the substrate. A nanostructure may be the functional component of an electronic device such as a gate-around-transistor device. In an embodiment of a gate-around-transistor, a nanowire ( 51 ) is supported by a substrate ( 50 ), the substrate being the drain, the nanowire the current channel and a top metal contact ( 59 ) the source. A thin gate dielectric ( 54 ) is separating the nanowire and the gate electrode ( 55 A, 55 B)

Integration substrate with a ultra-high-density capacitor and a through-substrate via

An integration substrate for a system in package comprises a through-substrate via and a trench capacitor wherein with a trench filling that includes at least 4 elec. conductive capacitor-electrode layers in an alternating arrangement with dielec. layers. The capacitor-electrode layers are alternatingly connected to a resp. one of 2 capacitor terminals provided on the 1st or 2nd substrate side. The trench capacitor and the through-substrate via are formed in resp. trench openings and via openings in the semiconductor substrate, which have an equal lateral extension exceeding 10 micro m. This structure allows, among other advantages, a particularly cost-effective fabrication of the integration substrate because the via openings and the trench openings in the substrate can be fabricated simultaneously. [on SciFinder (R)

Method of forming a nanocluster comprising dielectric layer and device comprising such a layer

A method of forming a dielectric layer (330) on a further layer (114, 320) of a semiconductor device (300) is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer (114, 320), the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei (335) within the dielectric layer (330) formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallicinnature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities. Such a dielectric layer is particularly suitable for use in semiconductor devices such as non-volatile memories

Planar, monolithically integrated coil

The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 [mu]H, and must have an equivalent series resistance of less than 0.1[Omega]. For this reason, those inductors are always bulky components, of a typical size of 221 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values

Planar, monolithically integrated coil

The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. Inmany applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 µH, and must have an equivalent series resistance of less than 0.1 O. For this reason, those inductors are always bulky components, of a typical size of 2 x 2 x 1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 veryhigh DC resistance values

DC-to-DC converter comprising a reconfigurable capacitor unit

The present invention relates to a configurable trench multi-capacitor device comprising a trench in a semiconductor substrate. The trench has a lateral extension exceeding 10 micrometer and a trench filling includes a number of at least four electrically conductive capacitor-electrode layers. A switching unit is provided that comprises a plurality of switching elements electrically interconnected between different capacitor-electrode layers of the trench filling. A control unit is connected with the switching unit and configured to generate and provide to the switching unit respective control signals for forming a respective one of a plurality of multi-capacitor configurations using the capacitor-electrode layers of the trench filling