Self-Consistent C-V Characterization of Depletion Mode Buried Channel InGaAs/InAs Quantum Well FET Incorporating Strain Effects

We investigated Capacitance-Voltage (C-V) characteristics of the Depletion Mode Buried Channel InGaAs/InAs Quantum Well FET by using Self-Consistent method incorporating Quantum Mechanical (QM) effects. Though the experimental results of C-V for enhancement type device is available in recent literature, a complete characterization of electrostatic property of depletion type Buried Channel Quantum Well FET (QWFET) structure is yet to be done. C-V characteristics of the device is studied with the variation of three important process parameters: Indium (In) composition, gate dielectric and oxide thickness. We observed that inversion capacitance and ballistic current tend to increase with the increase in Indium (In) content in InGaAs barrier layer.Comment: 5 pages, ICEDSA conference 201

In_xGa_{1-x}Sb MOSFET: Performance Analysis by Self Consistent CV Characterization and Direct Tunneling Gate Leakage Current

In this paper, Capacitance-Voltage (C-V) characteristics and direct tunneling (DT) gate leakage current of antimonide based surface channel MOSFET were investigated. Self-consistent method was applied by solving coupled Schr\"odinger-Poisson equation taking wave function penetration and strain effects into account. Experimental I-V and gate leakage characteristic for p-channel InxGa1-xSb MOSFETs are available in recent literature. However, a self- consistent simulation of C-V characterization and direct tunneling gate leakage current is yet to be done for both n- channel and p-channel InxGa1-xSb surface channel MOSFETs. We studied the variation of C-V characteristics and gate leakage current with some important process parameters like oxide thickness, channel composition, channel thickness and temperature for n-channel MOSFET in this work. Device performance should improve as compressive strain increases in channel. Our simulation results validate this phenomenon as ballistic current increases and gate leakage current decreases with the increase in compressive strain. We also compared the device performance by replacing InxGa1-xSb with InxGa1-xAs in channel of the structure. Simulation results show that performance is much better with this replacement.Comment: 7 pages, EIT 2012 IUPUI conferenc

High Electron Mobility Transistors: Performance Analysis, Research Trend and Applications

In recent years, high electron mobility transistors (HEMTs) have received extensive attention for their superior electron transport ensuring high speed and high power applications. HEMT devices are competing with and replacing traditional field‐effect transistors (FETs) with excellent performance at high frequency, improved power density and satisfactory efficiency. This chapter provides readers with an overview of the performance of some popular and mostly used HEMT devices. The chapter proceeds with different structures of HEMT followed by working principle with graphical illustrations. Device performance is discussed based on existing literature including both analytical and numerical models. Furthermore, some notable latest research works on HEMT devices have been brought into attention followed by prediction of future trends. Comprehensive knowledge of up‐to‐date results, future directions, and their analysis methodology would be helpful in designing novel HEMT devices

Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectrics for advanced complementary metal–oxide–semiconductor technology

We report a high-quality, ultrathin atomic-layer-deposited silicon–nitride/SiO2 stack gate dielectric. p+-polycrystalline silicon gate metal–oxide–semiconductor (MOS) capacitors with the proposed dielectrics showed enhanced reliability with respect to conventional SiO2. An exciting feature of suppressed soft-breakdown (SBD) events is observed in ramped voltage stressing which has been reconfirmed during time-dependent-dielectric breakdown measurements under constant field stressing. Introducing the idea of injected-carrier-induced localized physical damages resulting in the formation of conductive filaments near both Si/SiO2 and poly-Si/SiO2 interfaces, a model has been proposed to explain the SBD phenomena observed in the conventional SiO2 dielectrics. It is then consistently extended to explain the suppressed SBD in the proposed dielectrics. The reported dielectric can be a good choice to meet the urgent need for highly reliable ultrathin gate dielectrics in nanoscale complementary-MOS technology

Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal–oxide–semiconductor structures

A simple and effective method for the extraction of interface trap distribution in ultrathin metal– oxide–semiconductor (MOS) structures is presented. By a critical analysis of bipolar-pulse-induced currents through MOS capacitors, a technique is developed to determine the energy distribution of the interface traps without requiring the knowledge of surface potential and doping profile in the semiconductor. The proposed technique can be efficiently used to probe electrical stress, hot-carrier, and radiation-induced interfacial degradations in ultrathin MOS structures

NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability

Extremely thin (equivalent oxide thickness, Teq = 1.2 nm) silicon-nitride high-k (er = 7.2) gate dielectrics have been formed at low temperatures (<550 °C) by an atomic-layer-deposition (ALD) technique with subsequent NH3 annealing at 550 °C. A remarkable reduction in leakage current, especially in the low dielectric voltage region, which will be the operating voltage for future technologies, has made it a highly potential gate dielectric for future ultralarge-scale integrated devices. Suppressed soft breakdown events are observed in ramped voltage stressing. This suppression is thought to be due to a strengthened structure of Si–N bonds and the smoothness and uniformity at the poly-Si/ALD-silicon-nitride interface