The Effect of Fluorine on Low Temperature Boron Activation in Ultra Shallow Junctions

As CMOS device dimensions continue to shrink below 200nm, one of the major limiting factors in scaling size will become the drain and source junction depth. Using fluorine to create shallower p type junctions during ion implant is one way to decrease the junction depth. The effect of fluorine on the implant and subsequent anneal processes was studied. A low temperature annealing process was developed to decrease junction depths although sufficient dopant activation is being studied

Diffusion barrier cladding in Si/SiGe resonant interband tunneling diodes and their patterned growth on PMOS source/drain regions

Abstract—Si/SiGe resonant interband tunnel diodes (RITDs) employing-doping spikes that demonstrate negative differential resistance (NDR) at room temperature are presented. Efforts have focused on improving the tunnel diode peak-to-valley current ratio (PVCR) figure-of-merit, as well as addressing issues of manufacturability and CMOS integration. Thin SiGe layers sandwiching the B-doping spike used to suppress B out-diffusion are discussed. A room-temperature PVCR of 3.6 was measured with a peak current density of 0.3 kA/cmP. Results clearly show that by introducing SiGe layers to clad the B-doping layer, B diffusion is suppressed during post-growth annealing, which raises the thermal budget. A higher RTA temperature appears to be more effective in reducing defects and results in a lower valley current and higher PVCR. RITDs grown by selective area molecular beam epitaxy (MBE) have been realized inside of low-temperature oxide openings, with performance comparable with RITDs grown on bulk substrates. Index Terms—CMOS compatibilty, dopant diffusion, Ge-Si alloys, low-temperature oxide, molecular beam epitaxy, negative differential resistance, patterned growth, rapid thermal annealing, resonant interband tunneling diodes, silicon. I