Plasma enhanced chemical vapour deposited silicon carbide for back-end-of-line resistive memory

Resistive random-access memory (RRAM) are one of the most promising candidates for the next generation of memory technologies. Silicon Carbide-based memories are investigated in this thesis due to its heavy use as a back-end-of-the-line (BEOL) dielectric. This means that such devices could be fabricated directly on top of transistors, reducing the interconnect delay, and would be compatible with current commercial fabrication processes. This makes integration easier and cost effective. Our group has previously shown that Silicon Carbide-based RRAM show zero degradation up to 2MRad of γ irradiation. However, the fabrication process used yields devices with a low cyclability of around 10 switching cycles. Therefore, this thesis focuses on developing a new fabrication process that increases the performance and reliability of such memory cells. This is so that we can be assured that any measured failures in future life-time testing is due to the applied ion bombardment, instead of the inherent failures in the electronic properties of such a device. In this work I have developed a plasma enhanced chemical vapour deposition (PECVD) based SiC resistive memory which shows both volatile and non-volatile switching. The resistive memory devices showed reproducible and reliable switching across an entire 4-inch wafer. Both the On and Off state of the W/SiC/Cu devices were found to be dominated by Schottky emission with a change in the barrier height, which can be controlled with the applied voltage and number of sweeps. The volatile behaviour was characterised using varying pulse parameters and analyses of the change in conductance and the On state decay with time. The measured characteristics show emulation of short-term potentiation (STP) which takes place between the synapse of neurons. This work is the first to have a detailed analysis of STP in SiC-based RRAM memory cell. STP is understood to be key in information processing in the brain and this emulation can be used for brain-inspired computing. By varying the interval between 5ms and 30ms, we can further tune the peak conductance of our resistive memory cell and show that our decay between the input stimuli is in the order of milliseconds. The control in the conductance state is thought to be due to the ion migration caused by the applied pulses and the spontaneous diffusion of the conductive filament. It was also found that applying multiple STP potentiation and decay cycles showed that the overall peak conductance increased with cycle number. Therefore, taking a single conductance point of 181µS it was found that this specified conductance state could be re-learned exponentially quicker with each cycle, which has been seen in other neuromorphic based devices. The simple BEOL-compatible fabrication process and their ability to emulate STP functions in the brain make these memory cells a perfect candidate for embedded neuromorphic computing. I developed Si/SiC bilayer memory cells deposited by PECVD with 50nm of amorphousSi layer followed by a silicon rich 50nm of amorphous-SiC. These W/Si/SiC/Cu devices showed a similar switching mechanism to previously reported sputtered SiCbased dielectrics with the off state dominated by Schottky emission and the On state by Ohmic conduction. The Set and Reset voltages were measured to be around 2.1V and -0.8V respectively, with an average resistive ratio of 103 across 100 cycles. Using an external compliance current circuit, a pulsed measurement scheme was implemented to analyse the long-term endurance capabilities. Using a 200µs pulse, it is possible to Set and Reset the memory cells at 4V and -3V over a billion times. Analysing the average resistance and deviation across this billion cycle range, it was found that the memory cells showed no degradation and instead improved with cycle number. The endurance and stability is one of the highest recorded endurance for conductive bridge based resistive memory (CBRAM) and outperforms current commercially available RRAM devices targeted specifically for radiation hardened applications. These samples were also re-fabricated to determine if the devices were reproducible. These devices showed near identical inherent characteristics, displaying the reproducible fabrication process that was developed. This work presents the potential for a scalable and BEOL compatible embedded memory solution. Typically, high performance memory is fabricated in a Crosspoint array. In this work I have investigated the fabrication process flow for Crosspoint structures for the optimum device characteristics. I have also fabricated the first recorded SiC-based Crosspoint structure. By embedding cells using e-beam lithography and a SiO2 isolation layer, the endurance of the cells increased from 12 to over 100 cycles. Both devices exhibited high resistive ratio of around 106 , in keeping with previous SiC-based resistive memory. By analysing the read and write schemes across a 2x2 array, the sneakpath was investigated which showed the potential issues that can arise in the form of bit errors. This demonstrates how the high endurance memory cells that are developed require the use of a selector device when combined into a Crosspoint structure

Dataset supporting the publication "Reservoir computing using back-end-of-line SiC-based memristors"

Dataset supporting the publication &quot;Reservoir computing using back-end-of-line SiC-based memristors&quot;. This data demonstrates results of a back-end-of-line SiC-based memristor that exhibits short-term memory behaviour and is capable of encoding temporal signals. A physical reservoir computing system using our SiC-based memristor as the reservoir has been implemented. This physical reservoir computing system has been experimentally demonstrated to perform the task of pattern recognition. The results demonstrated good robustness to noisy pixels. The results indicate that our SiC-based memristor devices are strong contenders for potential applications in artificial intelligence, particularly in temporal and sequential data processing. The data includes 2 files: data.xlsx checkpoint.pt R. H. would like to thank the Royal Society for a Research Grant (RGS/R2/222171). O. K. thanks EPSRC and AWE Ltd for the ICASE studentship No. 16000087.</span