Platform Market Share of Korean Online Game under Two-Sided Market with Low Switching Costs

Online game is one of the fastest growing industries in Korea. It accounts for 5.8% of the world game market and one third of the world online game market. Korea’s online game market has two-sided market characteristic with very low switching costs. This paper is to study the various characteristics of two-sided market under low switching costs. We empirically investigate network externalities by using various variables in online game industry in Korea. We found the number of games available in a platform increased its market share, while the diversity of games and generality of games had no significant impacts. We also found that multi-homing increases an online platform’s market share when it is relatively new, but decreases market share when it becomes mature

Exploring the Combination of Organizational Improvisation and Organizational Learning in Information Systems Development

Organizational improvisation (OI) has been gaining an increasing attention to respond to rapidly changing environments, and it needs close and proper management. However, most of the findings on Improvisation I information system development studies are based on variance-based models. Thus, Du et al. (2019) propose a process model that features a continuous iteration between improvisational search and build in ISD. Their four-phase model describes continuous and iterative methods of organizational improvisation to respond to opportunities and threats, presenting an excellent step-by-step guideline for information system development managers to refer to from a practical standpoint. Despite the contributions, their exploratory research is not immune to limitations. Although the authors explained that learning is working in their model, there is only a fragmentary explanation of how the learning process works. In this work, we explore the boundary condition of Du et al.\u27s (2019) proposed model for the OI process in ISD then suggest a new model for ISD by combining the evaluation and learning process model proposed by Beynon-Davies et al. (2004), which is based on Argyris and Schon (1978). We believe that the new framework will help us apprehend that organizational improvisation in ISD generates short-term learning and long-term learning through the evaluation and learning from a process model perspective

The Effect of Emoji and Social Influence on Intervention for Misinformation on Social Media

Misinformation has spread rapidly through social media and recently become a concern. Accordingly, social media platforms have intervened to prevent the spread of misinformation, using such means as labeling photos or videos of misleading articles (i.e., “flagging”) and displaying links to fact-checking sites online. Although the development of various interventions can reduce the consumption of misinformation, it has not yet effectively controlled its spread. One factor that particularly influences individual decisions, namely, emojis accompanying articles on social media, has received little attention in the context of intervening in misinformation. I studied the effect of emojis on article believability and user engagement. Drawing on how emotions operate in social information theory, I built a research model and validated it using online experiments. I found that emojis affect readers\u27 belief in the article’s headline and behavior toward the article. Despite the warning message, a positive emoji leads readers to believe the article’s headline and engage further with it. Specifically, for groups that flagging affects less, positive emojis directly encourage readers to act on the article. This study contributes to the literature on the role and social influence of emojis as a medium of emotions, in the context of researching misinformation on social media and based on social influence literature, theories of emotion, and EASI theory. The findings can help social media policymakers design strategies to mitigate the spread of misinformation

A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration

A Novel Structure to Improve the Erase Speed in 3D NAND Flash Memory to Which a Cell-On-Peri (COP) Structure and a Ferroelectric Memory Device Are Applied

In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified. In the proposed structure, a hole is supplied to the channel through a pillar in the P+ crystal silicon sub-region located at the bottom of the 3D NAND flash structure to which the COP structure is applied. To verify this, we first confirmed that when the Gate Induced Drain Leakage (GIDL) erasing method used in the 3D NAND structure using the existing Charge Trap Flash (CTF) memory is applied as it is, the operation speed takes more than 10ms, for various reasons. Next, as a result of using the SP structure to solve this problem, even if the conventional erasing method was used until the thickness of the pillar was 20 nm, thanks to the rapidly supplied hole carriers, a fast-erasing rate of 1us was achieved. Additionally, this result is up to 10,000 times faster than the GIDL deletion method. Next, it was confirmed that when the pillar thickness is 10 nm, the erase operation time is greatly delayed by the conventional erasing method, but this can also be solved by appropriately adjusting the operating voltage and time. In conclusion, it was confirmed that, when the proposed SP structure is applied, it is possible to maximize the fast operation performance of the ferroelectric memory while securing the biggest advantage of the 3D NAND flash structure, the degree of integration

A Novel Structure and Operation Scheme of Vertical Channel NAND Flash with Ferroelectric Memory for Multi String Operations

In this study, the operation method of the proposed ferroelectric memory structure as a method to overcome the limitations of the existing Charge Trap Flash (CTF) memory Vertical NAND (V-NAND) structure was presented and verified through device simulation. The proposed structure and operation method applied the BiCS (Bit Cost Scalable) structure GIDL (Gate Induce Drain Leakage) deletion method to confirm that selective program operation is possible in the ferroelectric memory V-NAND (Vertical Channel NAND) structure. In particular, we confirmed that the proposed method can easily suppress the program operation by adjusting the hole density of the channel even in the “Y-mode” operation. The channel hole density adjustment that makes this possible can be easily controlled by the voltage difference between the bit line (BL) and drain select line (DSL) contacts. The proposed structure was verified through a device simulation, and as a result of the verification, it was confirmed that the channel hole can be selectively charged in the program operation. Through this, when the cell to be programmed shows the program operation of 2.3 V, the other cells do not. It was confirmed that it could be suppressed to 0.4 V

Floating Filler (FF) in an Indium Gallium Zinc Oxide (IGZO) Channel Improves the Erase Performance of Vertical Channel NAND Flash with a Cell-on-Peri (COP) Structure

In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation. The proposed FF structure can supply holes generated through the Gate-Induced Drain Leakage (GIDL) phenomenon in the upper polysilicon string select line (SSL) channel to the IGZO channel through a P-type filler, and the structure proposed by this operation shows a very fast erase speed of 4 μs. A fast erase speed was achieved because the filler adjacent to the IGZO channel, like IP structures in previous studies, functioned as a path through which electrons emitted from the charge storage layer moved easily, rather than simply supplying holes. This assumption was confirmed by assessing the change in electron density of the channel during the erase operation. Next, we investigated the optimum conditions for leakage current reduction through various condition changes of the lower ground select line (GSL) gate in the proposed structure. We confirmed that the leakage current of the proposed structure can be minimized by changing the number of lower GSL gates, changing the length of the GSL channel, and/or changing the work function of the GSL gate material. We obtained a leakage current of 10−17 A when the GSL channel was 480 nm long with six GSL gates, each with a length of 40 nm. The work function of the gates was 4.96 eV