Technology and layout-related testing of static random-access memories

Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology. However, there are certain technology and layout-related defects that are internal to the chip and are mostly time-dependent in nature. The resulting failures may or may not seriously degrade the input/output interface behavior. They may show up as electrical faults (such as a slow access fault) and/or functional faults (such as a pattern sensitive fault). However, these faults cannot be described properly with the functional fault models because these models do not take timing into account. Also, electrical fault models that describe merely the input/output interface behavior are inadequate to characterize every possible defect in the basic SRAM cell. Examples of faults produced by these defects are: (a) static data loss, (b) abnormally high currents drawn from the power supply, etc. Generating tests for such faults often requires a thorough understanding and analysis of the circuit technology and layout. In this article, we shall examine ways to characterize and test such faults. We shall divide such faults into two categories depending on the types of SRAMs they effect—silicon SRAMs and GaAs SRAMs.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/43015/1/10836_2004_Article_BF00972519.pd

BISRAMGEN: A silicon compiler for built-in self-repairable random-access memories.

This research focuses on a CAD tool, BISRAMGEN, that synthesizes layout geometries of built-in self-testable and built-in self-repairable single-port static and dynamic RAM modules with flexible, user-specified geometry parameters and CMOS design rules. Such a tool is of great importance in commercial microelectronics industry because it allows CAD designers to generate fault-tolerant RAM layouts very efficiently. Built-in self-repair (BISR) is an extremely cost-effective technique to enhance the manufacturing yield and field survivability of state-of-the-art integrated circuits employing deep submicron CMOS fabrication technology. BISR circuits not only increase the manufacturing yield and fault-tolerance of RAMs, but also allow them to be used in mission-critical field applications where diagnosing faults and performing replacements are too costly or impossible (such as space, avionic and oceanic applications). Furthermore, hard failures in embedded RAMs used in high-density microprocessors and ASICs cannot be repaired by other means due to the difficulty of accessing the internal nodes of the circuit. Currently, the task of incorporating such circuitry within embedded memories can be performed only manually or using semi-custom design techniques by the designer, and is thereby a major bottleneck in the design cycle. BISRAMGEN takes only about 10 minutes of CPU time on a DEC 3100 to build a 1 Mb static RAM array with 8 spare rows and the BIST/BISR circuitry. BISRAMGEN takes as input a high-level specification of the RAM parameters and the CMOS geometrical design rules, and builds an efficient built-in self-repairable RAM layout that is both drc and lvs-correct for the given ruleset (i.e., the layout satisfies the design rules for the chosen process and topologically agrees with the circuit schematic). BISRAMGEN uses a novel BIST approach based on the Inductive Fault Analysis (IFA) technique which guarantees a high physical defect coverage for CMOS RAMs. BISRAMGEN is design-rule independent; it can be used with a wide range of submicron CMOS processes developed by commercial microelectronics companies. It has been tested for processes supporting at least three layers of metal, with $\lambda$, the minimum feature size, ranging from 0.5 $\mu$m to 2.0 $\mu$m, and found to produce correct and efficient layouts. BISRAMGEN achieves a modest area overhead (typically less than 7%) for BIST, BISR and redundant elements combined, for a range of 10 representative CMOS processes with $\lambda$ varying from 0.5 $\mu$m to 2.0 $\mu$m. The area overhead achieved by BISRAMGEN is found to be comparable with or better than published results obtained using full-custom layout design. BISRAMGEN achieves a high yield of more than 95% with 10 spot defects scattered in the layout and a reliability of above 96% through 2 years of chip use. Furthermore, BISRAMGEN uses an innovative circuit technique for BISR (US patent pending) that guarantees effective zero delay overhead on RAM access time during normal operation. Existing BIST and BISR techniques are either associated with delay overhead (9) or use expensive circuit techniques that cause extra processing steps or more area overhead (54). (Abstract shortened by UMI.)Ph.D.Applied SciencesComputer scienceElectrical engineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/130213/2/9721957.pd

Data from: Morphological and phylogenetic evidences unveil a novel species of Gyroporus (Gyroporaceae, Boletales) from Indian Himalaya

Repeated macrofungal forays to East district of Sikkim followed by morphological and phylogenetic studies of collected wild mushrooms revealed an undescribed species, proposed here as Gyroporus paramjitii. This species is featured with hemispheric to plane dark brown to brownish orange pileus, concolorous or darker stipe, snow white to pale yellow pore surface which is immutable when bruised, 2- to 4-spored basidia, reniform to elliptic basidiospores, presence of pleurocystidia and cheilocystidia, absence of caulocystidia, trichoderm pattern of pileipellis and stipitipellis with encrusted erect hyphal elements and occurrence under Castanopsis sp. Macro- and micromorphological details coupled with phylogenetic analyses (based on nrITS and nrLSU data) are presented for this taxon

Gliophorus glutinosus sp. nov. (Hygrophoraceae, Agaricales) from Eastern Himalayan region of India

An interesting species of the genus Gliophorus (sect. Glutinosae), collected from Sikkim Himalaya in India, is described here as G. glutinosus sp. nov. after thorough morphological examination and phylogenetic analysis. The species is mainly characterised by its strongly glutinous basidiomata throughout, particularly on the twisted stipe, decurrent lamellae with glutinous edge, gelatinised cheilocystidia, presence of pleuropseudocystidia and absence of clamps in hyphae of the pileipellis. This communication includes detailed morphological description, illustrations, comparison with the allied taxa, nrITS based phylogeny of this novel taxon and a key to the species under Gliophorus sect. Glutinosae

Two new species and one new record of the genus Tylopilus (Boletaceae) from Indian Himalaya with morphological details and phylogenetic estimations

Volume: 33Start Page: 103End Page: 12

Gliophorus glutinosus sp. nov. (Hygrophoraceae, Agaricales) from Eastern Himalayan region of India

An interesting species of the genus Gliophorus (sect. Glutinosae), collected from Sikkim Himalaya in India, is described here as G. glutinosus sp. nov. after thorough morphological examination and phylogenetic analysis. The species is mainly characterised by its strongly glutinous basidiomata throughout, particularly on the twisted stipe, decurrent lamellae with glutinous edge, gelatinised cheilocystidia, presence of pleuropseudocystidia and absence of clamps in hyphae of the pileipellis. This communication includes detailed morphological description, illustrations, comparison with the allied taxa, nrITS based phylogeny of this novel taxon and a key to the species under Gliophorus sect. Glutinosae

A Combinatorial Optimization Problem for High Order PODs with Few Sensors

Experimental characterization of high dimensional dynamic systems sometimes uses the proper orthogonal decomposition (POD). If there are many measurement locations and relatively fewer sensors, then steady-state behavior can still be studied by sequentially taking several sets of simultaneous measurements. The number required of such sets of measurements can be minimized if we solve a combinatorial optimization problem. We aim to bring this problem to the attention of engineering audiences, summarize some known mathematical results about this problem, and present a heuristic (suboptimal) calculation that gives reasonable, if not stellar, results