14 research outputs found
Development and Performance of Kyoto's X-ray Astronomical SOI pixel (SOIPIX) sensor
We have been developing monolithic active pixel sensors, known as Kyoto's
X-ray SOIPIXs, based on the CMOS SOI (silicon-on-insulator) technology for
next-generation X-ray astronomy satellites. The event trigger output function
implemented in each pixel offers microsecond time resolution and enables
reduction of the non-X-ray background that dominates the high X-ray energy band
above 5--10 keV. A fully depleted SOI with a thick depletion layer and back
illumination offers wide band coverage of 0.3--40 keV. Here, we report recent
progress in the X-ray SOIPIX development. In this study, we achieved an energy
resolution of 300~eV (FWHM) at 6~keV and a read-out noise of 33~e- (rms) in the
frame readout mode, which allows us to clearly resolve Mn-K and
K. Moreover, we produced a fully depleted layer with a thickness of
. The event-driven readout mode has already been successfully
demonstrated.Comment: 7pages, 12figures, SPIE Astronomical Telescopes and Instrumentation
2014, Montreal, Quebec, Canada. appears as Proc. SPIE 9147, Space Telescopes
and Instrumentation 2014: Ultraviolet to Gamma Ra
A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure
This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e⁻rms, low dark current density of 56 pA/cm² at −35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV