FPGA Based Low Power ROM Design Using Capacitance Scaling

An ideal capacitor will not dissipate any power, but a real capacitor will have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM with frequencies (2.9GHz, 3.3GHz, 3.6GHz, 3.8GHz and 4.0GHz) supported by i7 processor.By using different capacitance there comes is reduction in I/O Power and Total power but not in other Powers like Clock, and Leakage (almost negligible). When capacitance goes from 30pF to 5pF, there is a saving of 28.12% occur in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog.</jats:p

Ambient Temperature Based Thermal Aware Energy Efficient ROM Design on FPGA

—Thermal aware design is currently gaining importance in VLSI research domain. In this work, we are going to design thermal aware energy efficient ROM on Virtex-5 FPGA. Ambient Temperature, airflow, and heat sink profile play a significant role in thermal aware hardware design life cycle. Ambient temperature is a temperature of surroundings. Airflow is measured in Linear Feet per Minute (LFM). Medium profile and high profile are two different heat sink profile available in XPower analyzer.When frequency goes from 4.0GHz to 1.0GHz, there is 21.8% reduction in clock power, 75% reduction in I/O Power, 35.6% reduction in leakage power and 53.8% reduction in total power at the same frequency.</jats:p