JESSI project: advanced technolgoy for 0.25 #mu#m CMOS and below. Subproject: process modules evaluation and integration. Theme 5 Multilevel metallization. Final report

Titanium- and cobaltdisilicide were investigated as material for shallow, low-resistive contacts in a CMOS-metallization system. ITM and DDS were used as self-aligned manufacturing processes. The TiSi_2- and CoSi_2-contact-systems were compared concerning manufacturing process and electrical and physical properties. The CoSi_2-contact-system shows the best properties. CVD-W was used to fill up vias and interconnects. To this a selective tungsten CVD process on CoSi_2 and a blanket deposition process were developed. Due to the excellent selectivity concerning the contact filling, a planarization effect was achieved. Accelerated tests show a high current-carrying capacity for the interconnects. Electromigration was identified as degradation mechanism. PECVD- and TEOS-PECVD-processes were investigated for the deposition of intermetal-dielectrics. An electrical and physical characterization of the layers have been performed. Processes with good step coverage and processes with a planarization effect were specified. Etch-back procedures using photo-resist and spin-on-techniques with various polyimides and a spin-on-glass were investigated in view of a planarization of the chip surface. The best results were achieved using the spin-on-technique with polyimide. (orig.)SIGLEAvailable from TIB Hannover: F94B1507+a+b / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekBundesministerium fuer Forschung und Technologie (BMFT), Bonn (Germany)DEGerman

Informationstechnologie: Schwerpunkt Submikron/Leitende Schichten Leitbahnen und Kontakte fuer grossintegrierte Schaltungen. Schlussbericht

With 35 refs., 20 tabs., 117 figs.Available from TIB Hannover: F93B199 / FIZ - Fachinformationszzentrum Karlsruhe / TIB - Technische InformationsbibliothekSIGLEDEGerman