Modeling, simulation and implementation of low power photovoltaic energy conversion system

Remote areas in India are still not connected to the power grid. But they have mobile network connectivity. The people face problems in charging their cell phones. They are forced to travel a long distances to get access to electrical outlets. This project focuses on providing a Photovoltaic System which could charge a cell phone battery. The developed system provides a solution to this problem. The system comprises of PV array, Maximum Power Point Tracker, Buck Converter and Charging Circuit. The system is modeled and simulated in Matlab-Simulink Environment. Hardware for the system is also implemented. We find proper synchronism between the results

Development of a Power-Efficient, Low Cost, and Flash FPGA Based On-Board Computer for Small-Satellites

On-Board Computers (OBCs) for Small-satellite missions are typically required to be designed using industrial grade Commercial-of-the-shelf (COTS) components due to budget constraints and short mission duration. The OBC must provide a variety of interfaces due to the diverse nature of COTS subsystems having different interface definitions. Traditional OBC designs with standard microcontrollers have fixed interfaces that require modification of the motherboard circuit/layout when the external interfaces require changes. Thus, a possible solution is to have an FPGA in-addition to the micro-controller thereby providing a configurable interface capability. System-on-Chip (SoC) devices that integrate a microcontroller with FPGA fabric provide an ideal solution for reducing the development time. Additionally, the limited availability of power in small satellite missions makes it essential to use power-efficient devices. Furthermore, single event upsets (SEUs) and single event latch-up (SELs) are a major problem for OBCs designed for Low Earth Orbit (LEO) small-satellite missions. Flash memory-based FPGAs provide the benefit of low power consumption and they are more also fault-tolerant due to their intrinsic robustness against induced single event upsets compared to SRAM-based FPGAs. This article describes the OBC developed using the flash-based Microsemi SmartFusion2 SoC FPGA as its key component, for the INSPIRESat-1 and INSPIRESat-2 small-satellite missions. The OBC is designed in two form factors one with 13cm x 10cm dimensions for INSPIRESat-1 and the other with 10cm x 10cm dimensions for INSPIRESat-2. The OBC uses a COTS System-on-Module (SoM) developed by Emcraft containing the SmartFusion2 SoC, which is mounted on a custom-designed motherboard containing other peripherals including flash memory, SD Cards, and an external watchdog timer. The OBC has a total power consumption of approximately 1 W, in the final flight configuration. The article here describes the architecture of the OBC in detail, the key features of which include multiple on-board memories, a multi-level reset methodology, and reconfigurable input/output interfaces. The article concludes with the details of comprehensive performance tests conducted on the INSPIRESat-1 OBC, which has qualified TRL-8 (technology readiness level) status after completing required environmental tests such as the Thermal Vacuum Test (TVAC) and vibration test as a part of the integrated satellite. INSPIRESat-2 was launched in January 2021 and due to the successful working of the OBC in fight it has achieved TRL-9 status through this mission. The OBC developed for INSPIRESat-1 is planned to achieve TRL-9 status after its launch in the third quarter of 2021

Carrier based Modulation Technique for Space Vector PWM of Dodecagonal Voltage SV Structures

Dodecagonal (12-sided polygon) voltage space vector structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lower switching frequency requirement making it more suitable for high power drive applications. A simple carrier based modulation method is proposed to obtain space vector pulse width modulation (SVPWM) switching patterns for a dodecagonal voltage space vector (SV) structure using only sampled reference voltages in this paper. The algorithm outputs the sector information and the SVPWM compare values which can be set as the references for any PWM module to obtain SVPWM switching sequences. The proposed method eliminates the need for partitioning and recombination of the computed timing values, angle estimation and computation of modulation index which in common in conventional SVPWM modulation technique. Simulation and experimental results are presented to validate the proposed method

A Voltage Space Vector Diagram Formed by Nineteen Concentric Dodecagons for Medium-Voltage Induction Motor Drive

In this paper, a multilevel dodecagonal voltage space vector structure with nineteen concentric dodecagons is proposed for the first time. This space vector structure is achieved by cascading two sets of asymmetric three-level inverters with isolated H-bridges on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of dc link voltages and switching states of the inverters. The proposed scheme retains all the advantages of multilevel topologies as well as the advantages of dodecagonal voltage space vector structure. In addition to that, a generic and simple method for calculation of pulsewidth modulation timings using only sampled reference values (v(alpha) and v(beta)) is proposed. This enables the scheme to be used for any closed-loop application such as vector control. In addition, a new method of switching technique is proposed, which ensures minimum switching while eliminating the fifth-and seventh-order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped wave-form for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady-state operation, transient operation, including start-up have been presented and the results of fast Fourier transform analysis is also presented for validating the proposed concept

Medium-Voltage Drive for Induction Machine With Multilevel Dodecagonal Voltage Space Vectors With Symmetric Triangles

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept

Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector (SV) structures have advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range including extreme 12-step operation, reduced device voltage ratings, lesser dv/dt stresses on devices and motor phase windings resulting in lower EMI/EMC problems, and lower switching frequency-making it more suitable for high-power drive applications. This paper proposes a simple method to obtain pulsewidth modulation (PWM) timings for a dodecagonal voltage SV structure using only sampled reference voltages. In addition to this, a carrier-based method for obtaining the PWM timings for a general N-level dodecagonal structure is proposed in this paper for the first time. The algorithm outputs the triangle information and the PWM timing values which can be set as the compare values for any carrier-based hardware PWM module to obtain SV PWM like switching sequences. The proposed method eliminates the need for angle estimation, computation of modulation indices, and iterative search algorithms that are typical in multilevel dodecagonal SV systems. The proposed PWM scheme was implemented on a five-level dodecagonal SV structure. Exhaustive simulation and experimental results for steady-state and transient conditions are presented to validate the proposed method

An Open-End winding IM drive with Multilevel 12-sided Polygonal Vectors with Symmetric Triangles

Multilevel inverters with hexagonal voltage space vector structures have improved performance of induction motor drives compared to that of the two level inverters. Further reduction in the torque ripple on the motor shaft is possible by using multilevel dodecagonal (12-sided polygon) voltage space vector structures. The advantages of dodecagonal voltage space vector based PWM techniques are the complete elimination of fifth and seventh harmonics in phase voltages for the full modulation range and the extension of linear modulation range. This paper proposes an inverter circuit topology capable of generating multilevel dodecagonal voltage space vectors with symmetric triangles, by cascading two asymmetric three level inverters with isolated H-Bridges. This is made possible by proper selection of DC link voltages and the selection of resultant switching states for the inverters. In this paper, a simple PWM timing calculation method is proposed. Experimental results have also been presented in this paper to validate the proposed concept

Timing Calculations for Three Level Dodecagonal Space Vector Structure From Reference Phase Voltages

A method to obtain pulse width modulation (PWM) timings for a three level dodecagonal (12-sided polygon) voltage space vector structure using only sampled reference values is proposed in this paper. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle to get the timings by using trigonometric calculations. This method requires look-up tables, angle estimation making it difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle within a sector. The proposed method does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. It is also is generic and can be extended to any number of levels with symmetric structures. The algorithm outputs the triangle number and the PWM compare values that can be used by any carrier based PWM module to obtain space vector PWM like switching sequences. Extensive simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method

Extending the Linear Modulation Range to the Full Base Speed Using a Single DC-Link Multilevel Inverter With Capacitor-Fed H-Bridges for IM Drives

In this paper, a new space vector pulse width modulation method to extend the linear modulation range of a cascaded five level inverter topology with a single dc supply is presented. Using this method, the inverter can be controlled linearly and the peak phase fundamental output voltage of the inverter can be increased from 0.577 to 0.637V(dc) without increasing the dc bus voltage and without exceeding the induction motor voltage rating. This new technique makes use of cascaded inverter pole voltage redundancy and property of the space vector structure for its operation. Using this, the induction motor drive can be operated till the full speed range (0-50 Hz) with the elimination of lower order harmonics in the phase voltage and phase current. The five-level topology presented in this paper is realized by cascading a two-level inverter and two full bridge modules with floating capacitors. The inverter topology and its operation for extending the modulation range is analyzed extensively. Simulation and experimental results for both steady-state and dynamic operating conditions are presented in this paper