Low-Power Mixed-Signal ASIC for Cryogenic SiPM Readout

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A low-power mixed-signal ASIC for SiPM readout at low temperature

A mixed-signal ASIC developed to readout silicon photomultipliers (SiPM) at low temperature is presented. The chip is designed in a 110 nm CMOS technology. Both sin- gle photon counting and Time-over-Threshold (ToT) operating modes are supported. The ToT modality is useful when many photons pile-up to yield a continuous signal. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power consumption is less tha 5 mW per channel. The architecture of a first 32-channel prototype is described. Dedicated test structures to qualify critical building blocks at cryogenic temperature have also been deployed

Integrated front-end electronics for single photon time-stamping in cryogenic dark matter detectors

ALCOR is a first prototype of a 32-pixel low-power mixed-signal ASIC developed to readout silicon photomultipliers at low temperature. The chip, designed in 110 nm CMOS technology, performs single photon time-stamping with a maximum event rate of 5 MHz per pixel. The time measurement is performed using low-power TDCs based on analogue time interpolation. The time binning achievable at maximum clock frequency is 50 ps and the target power consumption is less than 5 mW per pixel. Generated data are serialised and transmitted through LVDS drivers. To assert the CMOS electronic behaviour at 77K, a Test Chip has been produced and tested. Results of a digital synchronisation circuit are reported and discussed

A low-power mixed-signal ASIC for readout of SiPM at cryogenic temperature

ALCOR is a mixed-signal ASIC developed to readout silicon photomultipliers at low temperature. The chip is designed in a 110 nm CMOS technology. Both single photon counting and Time-over-Threshold operating modes are supported. In single photon counting mode an event rate of up to 5 MHz per channel can be accommodated. The time resolution is 50 ps and the target power consumption is less than 5 mW per channel. The architecture of a first 32-channel prototype is described. Dedicated test structures to qualify critical building blocks at cryogenic temperature are reported