DESIGN OF A GAAS DISTRIBUTED AMPLIFIER WITH LC TRAPS BASED BROADBAND LINEARIZATION

Increasing the linearity of power amplifiers has been an important area of research because its signal integrity influences the performance of the entire transreceiver system and there are strict regulatory requirements on them. Due to the nonlinear behaviour of power amplifiers, third order intermodulation products are generated close to the desired signals and cannot be removed by filters. Increasing linearity will help bring these distortion products closer to the noise floor. However, it is not an easy task to increase linearity without trading off output power. To maintain the same level of output power generated but with higher linearity, many techniques, each with its own pros and cons, have been implemented to linearize an amplifier. Techniques involving feedback are seriously limited in terms of modulation bandwidth whereas methods such as predistortion and feedforward are very difficult to implement. This project seeks to use a simple method of placing terminations directly to the distributed amplifier (DA), making it a device level linearization technique and can be used in addition to the other system level techniques mentioned earlier. To increase linearity over a broad bandwidth of 0.5 to 3.0 GHz, this work proposes using low impedance terminations (LC traps) at the envelope frequency to the input and output of several distributed amplifiers. This research is novel since this is the first time broadband improvement in linearity has been demonstrated using the LC trap method. Two design iterations were completed (first design iteration has four variants to test the output trap while the second design iteration has three variants to test the input trap). The low impedance terminations are implemented using inductor-capacitor networks that are external to the monolithic microwave integrated circuit (MMIC). Design and layout of the DAs were carried out using Agilent’s Advanced Design System (ADS). Results show that placing the traps at the output of the DA does not truly affect the linearity of the device at lower frequencies but provide an improvement of 1.6 dB and 3.4 dB to the third-order output intercept point (OIP3) at 2.5 GHz and 3.0 GHz, respectively. With traps at the input, measurement results at -5 dBm input power, viii 1.375 V base bias (61 mA total collector current) and 10 MHz two tone spacing show a broadband improvement throughout the band (0.5 GHz to 3.0 GHz) of 3.3 dB to 7.4 dB in OIP3. Furthermore, the OIP3 is increased to 19.2 dB above P1dB. Results show that the improvement in OIP3 comes without lowering gain, return loss or P1dB and without causing any stability problems

WIMAX TESTBED

WiMAX, the Worldwide Interoperability for Microwave Access, is a telecommunications technology aimed at providing wireless data over long distances in a variety of ways, from point-to-point links to full mobile cellular type access. It is based on the IEEE 802.16 standard, which is also called Wire IessMAN. The name WiMAX was created by the WiMAX Forum, which was formed in June 2001 to promote conformance and interoperability of the standard. The forum describes WiMAX as a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. This Final Year Project attempts to simulate via Simulink, the working mechanism of a WiMAX testbed that includes a transmitter, channel and receiver. This undertaking will involve the baseband physical radio link. Rayleigh channel model together with frequency and timing offsets are introduced to the system and a blind receiver will attempt to correct these offsets and provide channel equalization. The testbed will use the Double Sliding Window for timing offset synchronization and the Schmid! & Cox algorithm for Fractional Frequency Offset estimation. The Integer Frequency Offset synchronization is achieved via correlation of the incoming preamble with its local copy whereas Residual Carrier Fr~quency Offset is estimated using the L th extension method. A linear Channel Estimator is added and combined with all the other blocks to form the testbed. From the results, this testbed matches the standard requirements for the BER when SNR is 18dB or higher. At these SNRs, the receiver side of the testbed is successful in performing the required synchronization and obtaining the same data sent. Sending data with SNR lower than 18dB compromises its performance as the channel equalizer is non-linear. This project also takes the first few steps of hardware implementation by using Real Time Workshop to convert the Simulink model into C codes which run outside MATLAB. In addition, the Double Sliding Window and Schmid! & Cox blocks are converted to Xilinx blocks and proven to be working like their Simulink counterparts

WIMAX TESTBED

WiMAX, the Worldwide Interoperability for Microwave Access, is a telecommunications technology aimed at providing wireless data over long distances in a variety of ways, from point-to-point links to full mobile cellular type access. It is based on the IEEE 802.16 standard, which is also called Wire IessMAN. The name WiMAX was created by the WiMAX Forum, which was formed in June 2001 to promote conformance and interoperability of the standard. The forum describes WiMAX as a standards-based technology enabling the delivery of last mile wireless broadband access as an alternative to cable and DSL. This Final Year Project attempts to simulate via Simulink, the working mechanism of a WiMAX testbed that includes a transmitter, channel and receiver. This undertaking will involve the baseband physical radio link. Rayleigh channel model together with frequency and timing offsets are introduced to the system and a blind receiver will attempt to correct these offsets and provide channel equalization. The testbed will use the Double Sliding Window for timing offset synchronization and the Schmid! & Cox algorithm for Fractional Frequency Offset estimation. The Integer Frequency Offset synchronization is achieved via correlation of the incoming preamble with its local copy whereas Residual Carrier Fr~quency Offset is estimated using the L th extension method. A linear Channel Estimator is added and combined with all the other blocks to form the testbed. From the results, this testbed matches the standard requirements for the BER when SNR is 18dB or higher. At these SNRs, the receiver side of the testbed is successful in performing the required synchronization and obtaining the same data sent. Sending data with SNR lower than 18dB compromises its performance as the channel equalizer is non-linear. This project also takes the first few steps of hardware implementation by using Real Time Workshop to convert the Simulink model into C codes which run outside MATLAB. In addition, the Double Sliding Window and Schmid! & Cox blocks are converted to Xilinx blocks and proven to be working like their Simulink counterparts

Geometric and frequency scalable transistor behavioural model for MMIC design

This thesis presents research in developing and validating scaling in terms of geometry and frequency for Behavioural models in order to extend their functionality. Geometric and frequency scalability, once thought to be limited only to Physical and Compact models, greatly reduces the number of measurements for model generation. Besides saving precious time and effort, measurements do not need to be collected at high frequency or power levels, reducing the cost of purchasing measurement hardware. Scaling in terms of geometry is achieved by combining accurate measurement based non-linear look-up table models of a reference (smaller) transistor with the appropriate passive embedding networks. Experimental results show that the scalable model is successful in predicting the performance of devices up to 5 times larger in gate periphery on two separate Gallium Nitride wafers, one measured at 5 GHz and another at 9 GHz. This approach provides a robust utilization of Behavioural models by providing performance predictions at power levels beyond the limitations of high frequency measurement systems. The geometric scalable Behavioural model was also used in a CAD environment to help create a prototype single cell MMIC amplifier for operation at 5 GHz. Although the targeted performance was not achieved due to mismatch, the non-linear Behavioural model is still able to predict the performance of the actual fabricated circuit. The work in this thesis also introduces the first formulation and approach that enables Behavioural models to be frequency scalable. The experimental results T MINGHAO KOH ABSTRACT IV on HFETs from 2 different Gallium Nitride wafers measured from 2 GHz to 8 GHz (2 octaves), support theoretical analysis that frequency domain Behavioural models defined in the admittance domain have frequency scalable coefficients. Load-pull results show that the model can accurately predict nonlinear behaviour at frequencies that were not used during the model extraction process

Frequency-scalable nonlinear behavioral transistor model from single frequency X-parameters based on time-reversal transformation properties (INVITED)

This paper presents a powerful new method that generates a frequency-scalable nonlinear simulation model from single-frequency large-signal transistor X-parameter data. The method is based on a novel orthogonal identification (direct extraction) of current source and charge source contributions to the spectrally rich port currents under large-signal conditions. Explicit decomposition formulae, applied entirely in the frequency domain, are derived in terms of sensitivity functions at pairs of large-signal operating points related to one-another by time-reversal transformation. The method is applied and validated with respect to data from a measurement-based model of a pHEMT transistor. It is demonstrated that the scalable model can predict the nonlinear performance of the transistor over several orders of magnitude in frequency, all from X-parameters at a single fundamental frequency