Phenotypic and transcriptomic characterization of canine myeloid-derived suppressor cells

Myeloid-derived suppressor cells (MDSCs) are key players in immune evasion, tumor progression and metastasis. MDSCs accumulate under various pathological states and fall into two functionally and phenotypically distinct subsets that have been identified in humans and mice: polymorphonuclear (PMN)-MDSCs and monocytic (M)-MDSCs. As dogs are an excellent model for human tumor development and progression, we set out to identify PMN-MDSCs and M-MDSCs in clinical canine oncology patients. Canine hypodense MHC class II-CD5-CD21-CD11b+ cells can be subdivided into polymorphonuclear (CADO48A+CD14-) and monocytic (CADO48A-CD14+) MDSC subsets. The transcriptomic signatures of PMN-MDSCs and M-MDSCs are distinct, and moreover reveal a statistically significant similarity between canine and previously published human PMN-MDSC gene expression patterns. As in humans, peripheral blood frequencies of canine PMN-MDSCs and M-MDSCs are significantly higher in dogs with cancer compared to healthy control dogs (PMN-MDSCs: p < 0.001; M-MDSCs: p < 0.01). By leveraging the power of evolution, we also identified additional conserved genes in PMN-MDSCs of multiple species that may play a role in MDSC function. Our findings therefore validate the dog as a model for studying MDSCs in the context of cancer

Upgraded Readout and Digitizing System for the ATLAS Tile Calorimeter Demonstrator

During the shutdown of the ATLAS scintillating Tile calorimeter (TileCal) in 2013/14 one of its on-detector electronic modules will be replaced with a compatible hybrid module, which also serves as a demonstrator for future upgrades. This is being built to fulfill all requirements for the complete upgrade of the TileCal electronics in 2022 but augmented to stay compatible with the present system.\nWe describe a new Front End Board (FEB) that provides amplification and shaping, a Main Board that handles digitization and a high-speed communication Daughter Board. This system will permit us to acquire experience with a future fully digital readout system without disturbing the current analog trigger system

Development of a readout link board for the TileCal phase 2 demonstrator

The ATLAS Tile Calorimeter phase 2 upgrade demonstrator aims at installing a hybrid on-detector electronic system replacing 1-4 adjacent TileCal drawers in ATLAS starting end of phase 0, combining a fully functional phase 2 system with circuitry making it compatible with the present system. We are reporting a second generation prototype link and controller board connecting the drawer to off-detector electronics in USA-15. The new boards main logic component is a XILINX Kintex7 FPGA connected to an 12x5 Gb/s AVAGO opto transmitter and a 4x10 Gb/s QSFP+ connector. One of the latter will be chosen for the final design

Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and detector operation monitoring. We plan to insert one fully functional Demonstrator module into the present ATLAS TileCal detector for the LHC RUN 2 in August 2014

A Full Slice Test Version of a Tentative Upgraded Readout System for TileCal

The upgrade plans on the ATLAS hadronic calorimeter (TileCal) include the full readout of all data to the counting room. In order to study functional requirements of the future upgraded TileCal readout system we have assembled a minimal TDAQ slice. The aim is to implement a tentative readout chain for TileCal, starting with a newly developed 3-in-1 FE-board from University of Chicago and ending with the storage of triggered data on a PC. Later we will use PMT pulses, amplified and shaped by the 3-in-1 board, as a data source. However, for simplicity we start by using well defined calibration pulses also generated by the 3-in-1 board. The pulses are sampled by a 12 bit ADC, which is connected to an ML605 evaluation board from XILINX. These boards emulate the new on-detector electronics. The ML605 communicates via two 5Gb/s optical links with a Virtex-6 FPGA development board from HighTech Global which emulates the off-detector electronics. The off-detector board is situated in a PC and uses PCIe for readout and control. PCIe is a common ATCA protocol and ATCA will probably be the crate technology of choice. Using this setup we are able to test different parts, alone and together, which are critical for the further upgrade development. This would include new components, new firmware, clock distribution and recovery using the GBT-FPGA protocol as well as the development of software for monitoring and control. The critical function ality of the setup has been developed and tested separately. Charge injection pulses produced in the 3-in-1 card have been controlled and recorded by the ML605 FPGA. The GBT FPGA-FPGA link has been thoroughly tested. Finally we have also tested the PCIe transfer. After verifying the functionality of the full chain the aim is to successively replace parts in the testbed to increase the realism of the model. The next step will be to replace the ML605 with purpose developed circuit boards which may be considered as an early prototype

A prototype for the upgraded readout electronics of TileCal

Upgrade plans for ATLAS hadronic tile calorimeter (TileCal) include full readout of all data to the counting room. R&amp;amp;amp;D activities at different laboratories target different parts of the upgraded system. We are developing a possible implementation of the future readout electronics to be included in a full functional demonstrator. This must be capable of adapting to each of the three different front-end alternatives. Prototypes of the two PCBs that will be in charge of digitization, control and communication have been developed. The design is redundant and uses FPGAs with fault tolerant firmware for control and protocol conversion. Communication and clock synchronization between on and off detector electronics is implemented via high speed optical links using the GBT protocol