Impact of Displacement Defect Owing to Cosmic Rays on Three-Nanometer-Node Nanosheet FET 6T Static Random Access Memory

In this work, the effect of displacement defect (DD) owing to cosmic rays on six-transistor (6T) static random access memory (SRAM) with a 3 nm node nanosheet field-effect transistor (NSFET) is investigated using technology computer-aided design (TCAD) simulation. In order to comprehensively study the uncertainty of the radiation of NSFET 6T SRAM, the shape of the DD cluster cross-section and the transistor damaged by the DD in 6T SRAM are considered. Read static noise margin (RSNM) degradation (19 %) is the highest when the rectangular cross-section of the DD cluster (rectangular-DD cluster) is located in the pull-down1 (PD1) transistor. To mitigate the rectangular-DD cluster damage, we studied the variation in the DD cluster influence on the sheet shape and the source/drain (S/D) overlap length fluctuation. The sheet shape resulted in 2.3 % lower RSNM degradation in NS compared with nanowire (NW). Under the worst conditions (PD1 transistor damaged rectangular-DD cluster, NW structure), the S/D underlap structure showed 3.7 % lower RSNM degradation than the S/D overlap structure

Direct Growth Of Amorphous Silica Nanowires By Solid State Transformation Of Sio2 Films

Amorphous silica nanowires (a-SiONWs) were produced by direct solid state transformation from silica films. The silica nanowires grow on TiN/Ni/SiO 2/Si substrates during the annealing in H2 or a H 2:CH4 mixture at 1050°C. Titanium nitride (TiN) films were used to induce a solid state reaction with silica (SiO2) films on silicon wafers to provide silicon atoms into growing nanowires. The TiN layers induce the diffusion of silicon and oxygen to the surface by a stress gradient built inside the films. The nickel diffuses to the surface during the TiN deposition and acts as a nucleation site for the a-SiONWs. © 2003 Elsevier B.V. All rights reserved

Prediction of Statistical Distribution on Nanosheet FET by Geometrical Variability Using Various Machine Learning Models

Due to the aggressive scaling down of logic semiconductors, the difficulty of semiconductor component processes has increased. As the structure of components becomes more complex, the time and cost of processes and simulations have risen. Machine learning is now being used to analyze the electrical characteristics data of semiconductor components and apply the trained machine learning to next-generation semiconductor development. Machine learning trained on process data and simulation results can quickly and accurately predict which electrical characteristics change significantly when the component’s structure changes and which parameters have a significant impact on the electrical characteristic changes. This paper presents suitable machine learning models for analyzing and predicting the electrical characteristics (on-current ( $I_{on}$ ), off-current ( $I_{off}$ ), threshold voltage ( $V_{th}$ ), subthreshold swing (SS), and drain induced barrier lowering (DIBL)) and statistical distribution (mean and standard deviation of the electrical characteristics) resulting from geometrical variability (sheet thickness ( $T_{wire}$ ), sheet diameter ( $D_{wire}$ ), oxide thickness ( $T_{ox}$ ), gate length ( $L_{g}$ ), spacer length ( $L_{sp}$ ), gate metal work-function (WF)) in nanosheet field-effect transistor (NSFET), which are a next-generation logic device. Machine learning models, including regulation-based models (Ridge and LASSO) and tree-based models (decision tree (DT), random forest (RF), extreme gradient boost (XGBoost), and light gradient boost machine (LGBM)), are trained on technology computer-aided design (TCAD) simulation data. The LGBM more accurately predicts the electrical characteristics and statistical distribution of the NSFET than the other models. Additionally, we analyze the effect of geometrical variability on the NSFET based on feature importance