RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors

Abstract. Increasingly, embedded systems designers tend to use Application Specific Instruction Set Processors (ASIPs) during the design of application specific systems. However, one of the design metrics of embedded systems is the time to market of a product, which includes the design time of an embedded processor, is an important consideration in the deployment of ASIPs. While the design time of an ASIP is very short compared to an ASIC it is longer than when using a general purpose processor. There exist a number of tools which expedite this design process, and they could be divided into two: first, tools that automatically generate HDL descriptions of the processor for both simulation and synthesis; and second, tools that generate instruction set simulators for the simulation of the hardware models. While the first one is useful to measure the critical path of the design, die area, etc. they are extremely slow for simulating real world software applications. At the same time, the instruction set simulators are fast for simulating real world software applications, but they fail to provide information so readily available from the HDL models. The framework presented in this paper, RACE, addresses this issue by integrating an automatic HDL generator with a well-known instruction set simulator. Therefore, embedded systems designers who use our RACE framework will have the benefits of both a fast instruction set simulation and rapid hardware synthesis at the same time

Run-time energy-driven optimisation of embedded systems: a complete solution

Consumption of power and conservation of energy have become two of the biggest design challenges in construction of embedded systems. Energy is a resource in limited supply, but demands are increasing. Hence, much research is being performed to reduce power and energy usage or optimise performance under energy constraints.There are very few solutions that try to cater for the applications where the data input is not easily testable before run-time. These applications require an optimisation procedure that knows the power consumption of the system and is able to dynamically optimise operation to maximise performance while meeting energy constraints.This thesis provides a complete solution to the problem of run-time energy-driven optimisation of application performance. The complete system, from a processor that is able to provide feedback of the power consumption in parallel to execution, to applications that exploit the power feedback to provide dynamic optimisation.A processor that estimates its own power consumption is designed by the addition of small dedicated counters that tally occurrences of power consuming events which are macro modelled. The methodology is demonstrated on a standard processor achieving an average power estimation error of less than 2% while increasing area of the processor by only 5%.This enables energy-driven optimisation via application adaptation. Modification techniques and low-overhead algorithms are provided to demonstrate how energy feedback can be effectively used to maximise performance of algorithms within given constraints. Applications’ quality is maximised under given energy constraints using less than 0.02% of the execution time. Finally, the dissertation discusses the systems used to demonstrate the methodologies and techniques created throughout the research project. These implementations of the energy-driven optimisation system verify the soundness of the methods and applicability of the approaches used.This is the first time a complete solution for energy-driven optimisation has been shown, from creation of the processor to analysis of software utilising the approach. The methodologies and techniques can be applied to a variety of applications in a range of fields such as multimedia and networking that have never been possible before

Rapid Embedded Hardware/Software System Generation

This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30 % , energy consumed reduced by 24%, and performance improved by 24%. 1

Rapid embedded hardware/software system generation

This paper presents an RTL generation scheme for a SimpleScalar / PISA Instruction set architecture with system calls to implement C programs. The scheme utilizes ASIPmeister, a processor generation tool. The RTL generated is available for download. The second part of the paper shows a method of reducing the PISA instruction set and generating a processor for a given application. This reduction and generation can be performed within an hour, making this one of the fastest methods of generating an application specific processor. For five benchmark applications, we show that on average, processor size can be reduced by 30%, energy consumed reduced by 24%, and performance improved by 24%. © 2005 IEEE