Slickenside petrography: slip-sense indicators and classification

Petrographic study has been carried out on slickenside thin sections, to find out reliable microstructures for determining the slip-sense of faults, and to classify slickensides morphologically. Thin sections are made cut parallel to the striation and perpendicular to the slip plane. Many useful slip-sense indicators are found in thin section even though such indicators may be absent in hand specimens. They are (1) off-set or bending of once-continuous bodies such as veins, layers, grains or twin lamellae, (2) crystal fibers growing nearly parallel to the slip direction, (3) extensional fractures aligned oblique to the slip plane, (4) S-C geometries in ductile materials, and (5) Riedel- and P- shear fractures associated with the main slip surface. Two distinct layers may exist adjacent to the slickenside surface. One is termed coating: a discrete layer of material immediately under the slip surface. The other is termed the deformed host layer which is a zone of deformation in the host rock developed parallel to the slickenside. Slickensides are classified into four morphological types depending on the presence or absence of coating and deformed host layers. They are type A (deformed host layer only), type B (coating and deformed host layer), type C (no coating and no deformed host layer), and type D (coating only). This morphological classification can be a first step toward further genetic interpretation of slickensides, which could eventually be used to infer conditions of faulting. Possible development paths of each slickenside type indicate that present slickenside morphology can be influenced by rock type, slip-rate and depth of faulting during slip and by weathering and precipitation of veins along the pre-existing slip surface after slip. Although this classification is not yet fully satisfactory, it can perhaps be extended and improved by further systematic slickenside studies

CAD methodologies for low power and reliable 3D ICs

The main objective of this dissertation is to explore and develop computer-aided-design (CAD) methodologies and optimization techniques for reliability, timing performance, and power consumption of through-silicon-via(TSV)-based and monolithic 3D IC designs. The 3D IC technology is a promising answer to the device scaling and interconnect problems that industry faces today. Yet, since multiple dies are stacked vertically in 3D ICs, new problems arise such as thermal, power delivery, and so on. New physical design methodologies and optimization techniques should be developed to address the problems and exploit the design freedom in 3D ICs. Towards the objective, this dissertation includes four research projects. The first project is on the co-optimization of traditional design metrics and reliability metrics for 3D ICs. It is well known that heat removal and power delivery are two major reliability concerns in 3D ICs. To alleviate thermal problem, two possible solutions have been proposed: thermal-through-silicon-vias (T-TSVs) and micro-fluidic-channel (MFC) based cooling. For power delivery, a complex power distribution network is required to deliver currents reliably to all parts of the 3D IC while suppressing the power supply noise to an acceptable level. However, these thermal and power networks pose major challenges in signal routability and congestion. In this project, a co-optimization methodology for signal, power, and thermal interconnects in 3D ICs is presented. The goal of the proposed approach is to improve signal, thermal, and power noise metrics and to provide fast and accurate design space explorations for early design stages. The second project is a study on 3D IC partition. For a 3D IC, the target circuit needs to be partitioned into multiple parts then mapped onto the dies. The partition style impacts design quality such as footprint, wirelength, timing, and so on. In this project, the design methodologies of 3D ICs with different partition styles are demonstrated. For the LEON3 multi-core microprocessor, three partitioning styles are compared: core-level, block-level, and gate-level. The design methodologies for such partitioning styles and their implications on the physical layout are discussed. Then, to perform timing optimizations for 3D ICs, two timing constraint generation methods are demonstrated that lead to different design quality. The third project is on the buffer insertion for timing optimization of 3D ICs. For high performance 3D ICs, it is crucial to perform thorough timing optimizations. Among timing optimization techniques, buffer insertion is known to be the most effective way. The TSVs have a large parasitic capacitance that increases the signal slew and the delay on the downstream. In this project, a slew-aware buffer insertion algorithm is developed that handles full 3D nets and considers TSV parasitics and slew effects on delay. Compared with the well-known van Ginneken algorithm and a commercial tool, the proposed algorithm finds buffering solutions with lower delay values and acceptable runtime overhead. The last project is on the ultra-high-density logic designs for monolithic 3D ICs. The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high-density device integration at the individual transistor-level. The benefits and challenges of monolithic 3D integration technology for logic designs are investigated. First, a 3D standard cell library for transistor-level monolithic 3D ICs is built and their timing and power behavior are characterized. Then, various interconnect options for monolithic 3D ICs that improve design quality are explored. Next, timing-closed, full-chip GDSII layouts are built and iso-performance power comparisons with 2D IC designs are performed. Important design metrics such as area, wirelength, timing, and power consumption are compared among transistor-level monolithic 3D, gate-level monolithic 3D, TSV-based 3D, and traditional 2D designs.PhDCommittee Chair: Lim, Sung Kyu; Committee Member: Bakir, Muhannad; Committee Member: Kim, Hyesoon; Committee Member: Lee, Hsien-Hsin; Committee Member: Mukhopadhyay, Saiba