Highly Pipelined Asynchronous FPGAs

We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very ne-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can eciently take advantage of this large amount of pipelining. Our FPGA, which does not use a clock to sequence computations, automatically \selfpipelines " its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our FPGA ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300-400 MHz in a TSMC 0.25m process and 500-700 MHz in a TSMC 0.18m process

Programmable Asynchronous Pipeline Arrays

Abstract. We discuss high-performance programmable asynchronous pipeline arrays (PAPAs). These pipeline arrays are coarse-grain field programmable gate arrays (FPGAs) that realize high data throughput with fine-grain pipelined asynchronous circuits. We show how the PAPA architecture maintains most of the speed and energy benefits of a custom asynchronous design, while also providing post-fabrication logic reconfigurability. We report results for a prototype PAPA design in a 0.25µm CMOS process that has a peak pipeline throughput of 395MHz for asynchronous logic.

An Energy-Performance Metric for Mobile Ad hoc Networks

We discuss a joint energy-performance metric for mobile ad hoc networks. Previous work in ad hoc networks has concentrated on evaluating routing protocols for either high performance metrics or low energy metrics. The work in this paper evaluates routing protocols based on a metric that accounts for both energy and performance. We present a family of joint energy-performance metrics for ad hoc networks and show simulation results evaluating multiple protocols with various applications and network sizes. 1

Automated synthesis for asynchronous FPGAs

We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-level descriptions of asynchronous circuits into fine-grain asynchronous process netlists suitable for an AFPGA. The resulting circuits are inherently pipelined, and can be physically mapped onto our AFPGA with standard partitioning and place-and-route algorithms. For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the peak performance of the FPGA. Categories and Subject Descriptor

Energy-Efficient Pipelines

We discuss the design of energy-efficient pipelines for asynchronous VLSI architectures. To maximize throughput in asynchronous pipelines it is often necessary to insert buffer stages, increasing the energy overhead. Instead of optimizing pipelines for minimum energy or maximum throughput, we consider a joint energy-time metric of the form E , where E is the energy per operation and is the time per operation. We show that pipelines optimized for energy-time metric may need fewer buffer stages and we give bounds when such stages can be removed. We present several common asynchronous pipeline structures and their energy-time optimized solutions

The Derivation of Energy-Efficient Pipelines

We discuss the design of energy-efficient pipelines for asynchronous VLSI architectures. To maximize throughput in asynchronous pipelines it is often necessary to insert buffer stages, increasing the energy overhead. Instead of optimizing pipelines for minimum energy or maximum throughput, we consider a joint energy-time metric of the form�����, is the energy per and � operation is the time per operation. We show that pipelines optimized for energy-time metric may need where� fewer buffer stages and we give bounds when such stages can be removed. We present several common asynchronous pipeline structures and their energy-time optimized the����� solutions. 1