An 8-GHz beamforming transmitter IC in 130-nm CMOS

An 8-GHz beamforming transmitter IC has been designed in a 130-nm CMOS process. Two power amplifiers with independently controllable phase enable the beamforming. The phases are digitally controllable over the full 360° range, which is accomplished by binary weighting of quadrature phase signals in the power amplifiers. The quadrature phase signals are generated by a quadrature voltage controlled oscillator followed by a buffer, which serves as an isolation between the power amplifiers and the oscillator. The chip contains seven on-chip differential inductors, and consumes a total of 47 mA from a 1.0 V supply. The measured output power is -3 dBm for each power amplifier. © 2007 IEEE

60 GHz 130-nm CMOS Second Harmonic Power Amplifiers

Abstract—Two different frequency doubling power amplifiers have been measured, one with differential and one with singleended input, both with single-ended output at 60 GHz. The amplifiers have been implemented in a 1p8M 130-nm CMOS process. The resonant nodes are tuned to 30 GHz or 60 GHz using on-chip transmission lines, which have been simulated in ADS and Momentum. The measured input impedance of the single-ended PA is high at 250 Ω, and the differential input is similar, making the PA a suitable load for an oscillator in a fully integrated transmitter. The single-ended and differential input PA delivers 1 dBm and 3 dBm, respectively, of measured saturated output power to 50 Ω, both with a drain efficiency of 8%

A 90 nm CMOS 10 GHz beam forming transmitter

A 10 GHz beam forming transmitter was designed in a 90 nm CMOS process. Two power amplifiers with independently controllable phase enable the beam forming. The controllable phase is accomplished by switching in binary weighted transistors fed by quadrature signals, which are generated by a quadrature voltage controlled oscillator followed by a buffer. The design contains seven differential on-chip inductors, and consumes a total of 44.0 mA from a 1.2 V supply. The desired output power of 5 dBm per power amplifier is delivered at a power added efficiency of 22 % for the power amplifie

Second Harmonic 60-GHz Power Amplifiers in 130-nm CMOS

Two different frequency doubling power amplifier topologies have been compared, one with differential input and one with single-ended, both with single-ended output at 60 GHz. The frequency doubling capability is valuable from at least two perspectives, 1) the high frequency signal is on the chip as little as possible 2) the voltage controlled oscillator and power amplifier are at different frequencies easing the isolation of the two in a transceiver. The topologies have been simulated in a 1p8M 130-nm CMOS process. The resonant nodes are tuned with on-chip transmission lines. These have been simulated in ADS and compared to a standard Cadence component, tline3. The Cadence component gives a somewhat pessimistic estimation of the losses in the transmission line. The single ended input amplifier outputs a maximum of 3.7 dBm and draws 27 mA from a 1.2 V supply, while the one with differential input outputs 5.0 dBm and draws 28 mA. The 3-dB bandwidth of the amplifiers are 5.9 GHz and 6.8 GHz, respectively

Microwave CMOS Beamforming Transmitters

The increase of the consumer electronics market the last couple of decades has been one of the main drivers of IC process technology development. The majority of the ICs are used in digital applications, and for these CMOS is the choice of technology. The urge to squeeze more transistors on to a given area has led to shrinking feature sizes. It has resulted in higher transition frequencies and reduced supply voltage. During the last decade the increasing transition frequency has enabled CMOS to be used in RF applications, as well. Unfortunately, the decreasing supply voltage that, until recently, has accompanied the reduced feature sizes makes it more difficult to build power amplifiers that can deliver the amount of power needed to transmit the radio signal over the desired distance. In the receiver, the reduced supply voltage has resulted in reduced signal swing, which compromises linearity and dynamic range. In this thesis new topologies for the power amplifier is investigated, and the approach to combine the power from multiple power amplifiers is taken. In this way, despite the low supply voltage, the transmitted power by the IC can still be high. The increased transition frequency of CMOS technology can be used to increase the operating frequency to tens of GHz. The possibility for small sized phased antenna arrays then reveals, giving high directivity of the antenna and the potential for electrical beam steering. This both reduces interference to nearby receivers through spatial selectivity, and increases the equivalent isotropic radiated power. Power amplifiers with digital 360◦ phase control and antenna arrays have been investigated. In recent years applications at high operating frequencies have attained much focus from both academia and industry, such as automotive radar at 77 GHz andWLAN at 60 GHz. Even though the shrinking feature sizes of CMOS transistors have resulted in transit frequencies above 150 GHz, the high frequency required by many applications is still a great challenge for the CMOS designer. Therefore, in Paper IV and Paper VI different approaches to keep the on chip frequency lower than the RF carrier frequency as long as possible have been taken. In Paper IV two different frequency doubling 60 GHz power amplifier topologies are presented, and in Paper VI a subharmonic mixer with 30 GHz radio frequency and 15 GHz differential local oscillator is presented. Many transceiver architectures rely on quadrature signals driving the down- or upconversion mixers. The power amplifiers in Paper I and II need quadrature signals to implement the digital phase control. Therefore, in Paper V a three-stage active polyphase filter with quadrature output signals, high operation frequency, and wide bandwidth is analyzed. Analytical equations for both voltage gain and phase transfer function of a loaded stage are derived. The filter shows robustness against process parameter spread and achieves high quadrature signal quality from 6 GHz to 14 GHz

A Comparison of Two 10 GHz Beam Forming Transmitters, in 90 nm and 130 nm CMOS

A 10 GHz beam forming transmitter was designed in a 90 nm and a 130 nm CMOS process. Two power amplifers with independently controllable phase enable the beam forming. The controllable phase is accomplished by switching in binary weighted transistors fed by quadrature signals, which are generated by a quadrature voltage controlled oscillator followed by a buffer. The designs contain seven differential on-chip inductors. The 90 nm and 130 nm design consume a total of 44.0 mA and 52.1 mA, respectively, from a 1.2 V supply. The power amplifers deliver the desired output power of 5 dBm each at a power added effciency of 22% 90 nm and 18% 130 nm

A 30 GHz 90-nm CMOS Passive Subharmonic Mixer with 15 GHz Differential LO

A new passive subharmonic mixer topology is presented and compared to a previously published passive topology. The comparison is conducted using simulations at 30 GHz with a 90-nm CMOS design kit. The advantage of the new passive subharmonic mixer is that it only requires a differential local oscillator (LO) signal, compared to the previously published mixer that requires a quadrature LO signal. The mixer consists of two cascaded passive mixers with an interstage second order filter suppressing harmonics while providing some 10 dB of voltage gain at the LO frequency. The noise performance of the differential mixer is slightly worse than for the quadrature one, with a simulated down conversion SSB NF of 10 dB compared to 7 dB. The voltage conversion gain is - 1 dB for both mixers, all with a 1 V LO amplitude

Automotive Radar Transmitter at 24-GHz with Digital Beam Steering in 130-nm CMOS

In this paper simulations of a 130-nm CMOS 24-GHz automotive radar transmitter with digital beam steering is presented. The beam steering is performed by multiple PAs connected to separate antenna elements. The output phases of the PAs are individually controllable through 360◦ by binary weighting of quadrature phases. The circuit contains 18 PAs, each delivering 0 dBm to the antenna, resulting in a combined output power of 13 dBm. The 18 element antenna array will at 24 GHz be 11 cm, and have a directivity of 12 dB and a half power beam width of 5 degrees

Low power radio transmitter

A transmitter consisting of a voltage controlled oscillator (VCO) and power amplifier (PA) for the 400 MHz Medical Implanted Communication System band (MICS) was built in a standard 0.35-μm CMOS process. A push pull architecture was used for both the VCO and the PA. Two off-chip inductors were needed. The design was optimized for 400 μW output power at 3 V supply, which resulted in an efficiency of 26 %. This gives a total power consumption of 1.6 mW, of which the VCO uses about 0.3 mW

Antenna Array for a 24-GHz Automotive Radar with Dipole Antenna Element Patches

In this paper 3D electromagnetic simulations of an antenna array have been performed. The array is intended for automotive radar applications at 24 GHz. It is constructed from dipole antenna element patches, which are fed in the center by a differential signal. The dipole antenna element patches are simulated assuming a standard off the shelf substrate. They have a standing wave ratio less than 3 from 22.5 GHz to 24.5 GHz, when matched to 60Ohm. The directivity of the dipole patch is 9 dBi. The array consists of 24 elements giving it a physical size of 150 mm, with a groundplane of 200×100 mm2. An antenna of that size is easy to integrate in a car. Beam steering can be accomplished by changing the phases of the signals to the different elements [1], thus making the arrangement mechanically robust since the antenna does not have to move. The directivity for the antenna array is larger than 9.4 dBi for a steering angle of ±7◦ and the half power beam width is smaller than 6◦ over the same steering angle