9 research outputs found

    Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications

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    The feasibility of medium-high fraction SiGe based FinFET pMOS devices for a sub-10nm CMOS logic technology from a performance (IEFF @ fixed IOFF) standpoint is evaluated, considering three key device aspects-stress, band-to-band-tunneling (BTBT), and interface charge density (DIT). The analysis reveals that while for high Ge (>90%), performance is limited by BTBT, overall stress reduction beyond Ge 65% further limits performance. Including realistic (DIT) profile further shows that optimum Ge content is between 40%???50% for low power applications. ?? 2016 IEEE

    Aryl Hydrocarbon Receptor: Its Regulation and Roles in Transformation and Tumorigenesis

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    Management von Netzwerkorganisationen – Zum Stand der Forschung

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    Utilization of Satellite-based Digital Elevation Model (DEM) for Hydrologic Applications: A Review

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