Efficient Arguments and Proofs for Batch Arithmetic Circuit Satisfiability

In this paper, we provide a systematic treatment for the batch arithmetic circuit satisfiability and evaluation problem. Building on the core idea which treats circuit inputs/outputs as a low-degree polynomials, we explore various interactive argument and proof schemes that can produce succinct proofs with short verification time. In particular, for the batch satisfiability problem, we provide a construction of succinct interactive argument of knowledge for generic log-space uniform circuits based on the bilinear pairing and common reference string assumption. Our argument has size in $O(poly(\lambda) \cdot (|\mathbf{w}| + d \log |C|))$, where $\lambda$ is the security parameter, $|\mathbf{w}|$ is the size of the witness, and $d$ and $|C|$ are the depth and size of the circuit, respectively. Note that the argument size is independent of the batch size. To the best of our knowledge, asymptotically it is the smallest among all known batch argument schemes that allow public verification. The batch satisfiablity problem simplifies to a batch evaluation problem when the circuit only takes in public inputs (i.e., no witness). For the evaluation problem, we construct statistically sound interactive proofs for various special yet highly important types of circuits, including linear circuits, and circuits representing sum of polynomials. Our proposed protocols are able to achieve proof sizes independent of the batch size. We also describe protocols optimized specifically for batch FFT and batch matrix multiplication which achieve desirable properties, including lower prover time and better composability. We believe these protocols are of interest in their own right and can be used as primitives in more complex applications

Comparing gene discovery from Affymetrix GeneChip microarrays and Clontech PCR-select cDNA subtraction: a case study

BACKGROUND: Several high throughput technologies have been employed to identify differentially regulated genes that may be molecular targets for drug discovery. Here we compared the sets of differentially regulated genes discovered using two experimental approaches: a subtracted suppressive hybridization (SSH) cDNA library methodology and Affymetrix GeneChip(® )technology. In this "case study" we explored the transcriptional pattern changes during the in vitro differentiation of human monocytes to myeloid dendritic cells (DC), and evaluated the potential for novel gene discovery using the SSH methodology. RESULTS: The same RNA samples isolated from peripheral blood monocyte precursors and immature DC (iDC) were used for GeneChip microarray probing and SSH cDNA library construction. 10,000 clones from each of the two-way SSH libraries (iDC-monocytes and monocytes-iDC) were picked for sequencing. About 2000 transcripts were identified for each library from 8000 successful sequences. Only 70% to 75% of these transcripts were represented on the U95 series GeneChip microarrays, implying that 25% to 30% of these transcripts might not have been identified in a study based only on GeneChip microarrays. In addition, about 10% of these transcripts appeared to be "novel", although these have not yet been closely examined. Among the transcripts that are also represented on the chips, about a third were concordantly discovered as differentially regulated between iDC and monocytes by GeneChip microarray transcript profiling. The remaining two thirds were either not inferred as differentially regulated from GeneChip microarray data, or were called differentially regulated but in the opposite direction. This underscores the importance both of generating reciprocal pairs of SSH libraries, and of real-time RT-PCR confirmation of the results. CONCLUSIONS: This study suggests that SSH could be used as an alternative and complementary transcript profiling tool to GeneChip microarrays, especially in identifying novel genes and transcripts of low abundance

Design of thermal monitoring infrastructures and thermal optimizations for high performance chips

The computation capability of the integrated chips has been elevated constantly as a result of aggressive technology scaling. However, as a companion, the heat dissipation of the high-performance chips keeps increasing, causing thermal variation in both temporal and spatial terms. The impact of temperature on integrated chips is multifaceted. High temperature degrades the reliability and increases the leakage power of the chips. Temperature also has a complex implication on circuit timing, introducing new challenges in the circuit synthesis and verification flow. Resolving these thermal issues requires a comprehensive treatment across multiple design levels. In this dissertation, we propose such a multilevel treatment. The three key aspects of our treatment is monitoring, mitigation and utilization. Thermal monitoring mechanisms constitute our system level approach, which plays an essential role for thermal emergency prediction, detection, and prevention. Accuracy is the essential goal for the design of the thermal monitoring system. We factorize the sources of the monitoring inaccuracy into three parts: (1) inaccuracy due to the placement of the sensing devices, (2) inaccuracy due to the routing infrastructure, and (3) inaccuracy due to the precision of the sensing devices. Correspondingly, we have proposed three design methodologies/concepts to diminish these three sources. These techniques include (1) non-uniform and uniform sensor placement strategies, (2) a sensor routing infrastructure which supports 4-wire (Kelvin) voltage measurement, and (3) an Integrated On-chip Thermocouple Array (IOTA). Thermal mitigation is the microarchitecture level solution, which aims to resolve the thermal emergencies by effectively removing the heat out of the hotspots. To achieve efficient heat mitigation, we investigate on on-chip active cooling technology that employs miniature thermoelectric heat pumps. We indentify the design constraints and trade-offs for an on-chip thermoelectric cooling system. In order to examine the cooling system, we established a novel theoretical analysis framework which extends the theory of inverse-positive matrix and the eigenvalue/eigenvector theory in linear algebra. Built on this theoretical foundation, we propose a systematic optimization scheme to maximize the efficiency of the cooling system. Thermal utilization is our RTL/gate level therapy, which exploits the temperature fluctuations in both temporal and spatial terms to guarantee timing closure. Instead of viewing temperature fluctuations as adverse effects, we treat temperature as a dimension of timing optimization and temperature dependent timing slacks as manageable resources. Our proposed utilization techniques include (1) a self-adjusting clock tree architecture (SACTA), and (2) a synergistic Vth assignment and clock skew scheduling technique

Large Language Model Guided Tree-of-Thought

In this paper, we introduce the Tree-of-Thought (ToT) framework, a novel approach aimed at improving the problem-solving capabilities of auto-regressive large language models (LLMs). The ToT technique is inspired by the human mind's approach for solving complex reasoning tasks through trial and error. In this process, the human mind explores the solution space through a tree-like thought process, allowing for backtracking when necessary. To implement ToT as a software system, we augment an LLM with additional modules including a prompter agent, a checker module, a memory module, and a ToT controller. In order to solve a given problem, these modules engage in a multi-round conversation with the LLM. The memory module records the conversation and state history of the problem solving process, which allows the system to backtrack to the previous steps of the thought-process and explore other directions from there. To verify the effectiveness of the proposed technique, we implemented a ToT-based solver for the Sudoku Puzzle. Experimental results show that the ToT framework can significantly increase the success rate of Sudoku puzzle solving. Our implementation of the ToT-based Sudoku solver is available on GitHub: \url{https://github.com/jieyilong/tree-of-thought-puzzle-solver}

Automated design of self-adjusting pipelines

We propose a self-adjusting pipeline structure to enhance chip performance and robustness considering the effects of process variations. We achieve this by introducing delay sensors to monitor internal timing violations within a pipeline stage and variable clock skew buffers to adjust the timing of the pipeline stage based on the feedback from the delay sensors. Furthermore, we formulate the delay sensor insertion and variable clock skew configuration problem as a stochastic mixed-integer programming problem and propose a simulated-annealing based algorithm to solve it. A comparison between the designs with and without the self-adjusting enhancement reveals that, we are able to improve the average performance of a batch of chips by 9.5%