Hardware Acceleration for Similarity Measurement in Natural Language Processing

Abstract-The continuation of Moore's law scaling, but in the absence of Dennard scaling, motivates an emphasis on energyefficient accelerator-based designs for future applications. In natural language processing, the conventional approach to automatically analyze vast text collections-using scale-out processingincurs high energy and hardware costs since the central computeintensive step of similarity measurement often entails pair-wise, allto-all comparisons. We propose a custom hardware accelerator for similarity measures that leverages data streaming, memory latency hiding, and parallel computation across variable-length threads. We evaluate our design through a combination of architectural simulation and RTL synthesis. When executing the dominant kernel in a semantic indexing application for documents, we demonstrate throughput gains of up to 42× and 58× lower energy per similaritycomputation compared to an optimized software implementation, while requiring less than 1.3% of the area of a conventional core

CNS-LAND score: predicting early neurological deterioration after intravenous thrombolysis based on systemic responses and injury

ImportanceEarly neurological deterioration (END) is a critical complication in acute ischemic stroke (AIS) patients receiving intravenous thrombolysis (IVT), with a need for reliable prediction tools to guide clinical interventions.ObjectiveThis study aimed to develop and validate a rating scale, utilizing clinical variables and multisystem laboratory evaluation, to predict END after IVT.Design, setting, and participantsThe Clinical Trial of Revascularization Treatment for Acute Ischemic Stroke (TRAIS) cohort enrolled consecutive AIS patients from 14 stroke centers in China (Jan 2018 to Jun 2022).OutcomesEND defined as NIHSS score increase >4 points or death within 24 h of stroke onset.Results1,213 patients (751 in the derivation cohort, 462 in the validation cohort) were included. The CNS-LAND score, a 9-point scale comprising seven variables (CK-MB, NIHSS score, systolic blood pressure, LDH, ALT, neutrophil, and D-dimer), demonstrated excellent differentiation of END (derivation cohort C statistic: 0.862; 95% CI: 0.796–0.928) and successful external validation (validation cohort C statistic: 0.851; 95% CI: 0.814–0.882). Risk stratification showed END risks of 2.1% vs. 29.5% (derivation cohort) and 2.6% vs. 31.2% (validation cohort) for scores 0–3 and 4–9, respectively.ConclusionCNS-LAND score is a reliable predictor of END risk in AIS patients receiving IVT

Cooperative caching for chip multiprocessors

Chip multiprocessor (CMP) systems have made the on-chip caches a critical resource shared among co-scheduled threads. Limited off-chip bandwidth, increasing on-chip wire delay, destructive inter-thread interference, and diverse workload characteristics pose key design challenges. To address these challenge, we propose CMP cooperative caching (CC), a unified framework to efficiently organize and manage on-chip cache resources. By forming a globally managed, shared cache using cooperative private caches. CC can effectively support two important caching applications: (1) reduction of average memory access latency and (2) isolation of destructive inter-thread interference. CC reduces the average memory access latency by balancing between cache latency and capacity opti-mizations. Based private caches, CC naturally exploits their access latency benefits. To improve the effective cache capacity, CC forms a “shared ” cache using replication control and LRU-based global replacement policies. Via cooperation throttling, CC provides a spectrum of caching behaviors between the two extremes of private and shared caches, thus enabling dynamic adaptation to suit workload requirements. We show that CC can achieve a robust performance advantage over private and shared cache schemes across different processor, cache and memory configurations, and a wide selection of multithreaded and multiprogramme

Application of Computer Simulation Optimization Algorithm in Waste Treatment of Drilling Engineering

The existing computer technology is used to conduct an in-depth study and analysis of drilling waste treatment, and the results are analyzed by computer simulation optimization algorithms. Based on the system theory, we define the research system, combine the unique characteristics of the technological innovation mechanism of drilling waste treatment, and use the internal and external factors affecting the technological innovation dynamics of drilling waste treatment, such as drilling waste treatment capacity, from the current actual situation. On this basis, factor analysis is used to analyze the factors affecting technological innovation dynamics from both internal and external aspects of the system, establish a system model of technological innovation dynamics of drilling waste disposal, and give the initial values of the simulation model. This will reduce the pollution of the environment and enhance the competitiveness of enterprises. Drilling waste treatment technology is getting increased attention, but at this stage, there is no suitable technology innovation mechanism for drilling waste treatment. Through the simulation trend chart obtained by sensitivity analysis, the key factors in the system are found, and the innovation power mechanism of drilling waste treatment technology is constructed, which provides a basis for the formulation of enterprise technological innovation strategies and the development of technological innovation activities. Research on the dynamic mechanism of drilling waste treatment technology innovation explores a waste treatment mechanism suitable for the drilling industry, so as to promote the steady development of the drilling industry and at the same time provide theoretical support for the treatment of drilling engineering waste

More on Conjunctive Selection Condition and Branch Prediction

Traditionally, database applications have focused on the parameters of the disk devices to optimize performance. As the memory and caches get bigger, a larger fraction of the data can be stored in memory and caches. For applications where substantial data can be present in the memory, other optimizations which consider processor and memory characteristics can also be applied effectively. In this report, we re-examine the effect of branch predictions on conjunctive selection conditions, for both current and future CPU designs. Our simulation results show that branch prediction does degrade the performance significantly, especially in future processors, which will have higher arithmetic computation bandwidth and branch misprediction penalty. No optimizer will be needed for choosing amongst conjunctive selection plans, since the strategy using no branches will always perform better. I

Submitted for publication Dynamic Architecture-Based Monitoring

Increasingly, systems need to have the ability to adapt at runtime. In the past, system adaptation has been coded into each application, making it costly to modify the adaptation policy or mechanism, difficult to reuse in other applications, hard to reason about, and obfuscates the primary application code. In this paper we outline an approach that addresses these problems by externalizing adaptation mechanisms. Specifically, we describe mechanisms for observing a running system, interpreting these observations according to the system’s architecture, analyzing the system architecture to ascertain if it still meets its design constraints, triggering repair strategies to repair the architecture if not, and applying these architectural changes to the running system. We discuss the design of such a system, and focusing on our research into providing a monitoring infrastructure that can be independently applied to a variety of systems. We also describe our tool support for interpreting and displaying observations according to an architectural description of the system written in Acme.